Datasheet SN74LVT125D, SN74LVT125DBLE, SN74LVT125DBR, SN74LVT125DR, SN74LVT125PWLE Datasheet (Texas Instruments)

SN54LVT125, SN74LVT125

3.3-V ABT QUADRUPLE BUS BUFFERS
WITH 3-STATE OUTPUTS

SCBS133D – MA Y 1992 – REVISED JULY 1995

D

State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation

D

Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)

D

Support Unregulated Battery Operation
Down to 2.7 V

D

Typical V
< 0.8 V at V

D

ESD Protection Exceeds 2000 V Per

(Output Ground Bounce)

OLP

= 3.3 V, TA = 25°C

CC

MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17

D

Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors

D

Support Live Insertion

D

Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (J) DIPs

description

SN54LVT125...J PACKAGE

SN74LVT125. . . D, DB, OR PW PACKAGE

1Y

NC

2OE

NC

2A

NC – No internal connection

(TOP VIEW)

14

1

1OE

2

1A

3

1Y

4

2OE

5

2A

6

2Y

GND

SN54LVT125. . . FK PACKAGE

7

(TOP VIEW)

1A

1OE

3212019

4
5
6
7
8

910111213

2Y

GND

13
12
11
10

NC

NC

9
8

CC

V

3Y

V

CC

4OE
4A
4Y
3OE
3A
3Y

4OE

18
17
16
15
14

3A

4A
NC
4Y
NC
3OE

These bus buffers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to
provide a TTL interface to a 5-V system environment.

The ′LVT125 feature independent line drivers with 3-state outputs. Each output is in the high-impedance state
when the associated output-enable (OE) input is high.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
T o ensure the high-impedance state during power up or power down, OE

should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74L VT125 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count

and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54L VT125 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74LVT125 is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1995, Texas Instruments Incorporated

1

SN54LVT125, SN74LVT125

3.3-V ABT QUADRUPLE BUS BUFFERS
WITH 3-STATE OUTPUTS

SCBS133D – MA Y 1992 – REVISED JULY 1995

OE A

FUNCTION TABLE

(each buffer)

INPUTS

L H H
L LL

H X Z

OUTPUT

Y

1
2
4
5

10
9

13
12

†

1

EN

3

6

8

11

logic diagram (positive logic)

1

23

1A 1Y

4

56

2A 2Y

10

98

3A 3Y

13

12 11

4A 4Y

1Y

2Y

3Y

4Y

1OE

2OE

3OE

4OE

logic symbol

1OE

1A

2OE

2A

3OE

3A

4OE

4A

†

This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.

Pin numbers shown are for the D, DB, J, and PW packages.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V
Voltage range applied to any output in the high state or power-off state, V

Current into any output in the low state, IO: SN54LVT125 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the high state, I
Input clamp current, I

Output clamp current, I

Maximum power dissipation at TA = 55°C (in still air) (see Note 3):D package 1.25 W. . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and VO > VCC.

3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the

Data Book

, literature number SCBD002B.

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Note 1) –0.5 V to 7 V. . . .

O

SN74LVT125 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): SN54LVT125 48 mA. . . . . . . . . . . . . . . . . . . . . . . . .

O

SN74LVT125 64 mA. . . . . . . . . . . . . . . . . . . . . . . . .

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

O

DB or PW package 0.5 W. . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Package Thermal Considerations

application note in the 1994

ABT Advanced BiCMOS T echnology

‡

2

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UNIT

PARAMETER

TEST CONDITIONS

UNIT

V

V

V

3 V

V

V

V

V

V

V

I

A

Data inputs

I

V

V

Data inputs

A

I

CC

mA

SN54LVT125, SN74LVT125

3.3-V ABT QUADRUPLE BUS BUFFERS
WITH 3-STATE OUTPUTS

SCBS133D – MA Y 1992 – REVISED JULY 1995

recommended operating conditions (see Note 4)

SN54LVT125 SN74LVT125

MIN MAX MIN MAX

V

CC

V

IH

V

IL

V

I

I

OH

I

OL

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
T

A

NOTE 4: Unused control inputs must be held high or low to prevent them from floating.

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

§

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

Supply voltage 2.7 3.6 2.7 3.6 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 5.5 5.5 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA

Operating free-air temperature –55 125 –40 85 °C

SN54LVT125 SN74LVT125

MIN TYP†MAX MIN TYP†MAX

V

IK

OH

OL

I

I

off

I(hold)

I

OZH

I

OZL

∆I

CC

C

i

C

o

VCC = 2.7 V, II = –18 mA –1.2 –1.2 V
VCC = MIN to MAX‡, IOH = –100 µA VCC–0.2 VCC–0.2
VCC = 2.7 V, IOH = – 8 mA 2.4 2.4

=

CC

= 2.7

CC

= 3

CC

VCC = 0 or MAX‡, VI = 5.5 V 10 10

VCC = 3.6 V

VCC = 0, VI or VO = 0 to 4.5 V ±100 µA

= 3

CC

VCC = 3.6 V, VO = 3 V 5 5 µA
VCC = 3.6 V, VO = 0.5 V –5 –5 µA

VCC = 3.6 V, IO = 0,
VI = VCC or GND

VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,

§
Other inputs at VCC or GND

VI = 3 V or 0 4 4 pF
VO = 3 V or 0 8 8 pF

IOH = – 24 mA 2
IOH = –32 mA 2
IOL = 100 µA 0.2 0.2
IOL = 24 mA 0.5 0.5
IOL = 16 mA 0.4 0.4
IOL = 32 mA 0.5 0.5
IOL = 48 mA 0.55
IOL = 64 mA 0.55

VI = VCC or GND Control inputs ±1 ±1
VI = V

CC

VI = 0

VI = 0.8 V
VI = 2 V

p

p

Outputs high 0.12 0.19 0.12 0.19
Outputs low 4.5 7 4.5 7
Outputs

disabled

75 75

–75 –75

0.12 0.19 0.12 0.19

1 1

–5 –5

0.3 0.2 mA

µ

µ

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

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3

SN54LVT125, SN74LVT125

A

Y

ns

OE

Y

ns

OE

Y

ns

3.3-V ABT QUADRUPLE BUS BUFFERS
WITH 3-STATE OUTPUTS

SCBS133D – MA Y 1992 – REVISED JULY 1995

switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)

SN54LVT125 SN74LVT125

PARAMETER

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

†

PLZ

All typical values are at VCC = 3.3 V, TA = 25°C.

FROM

(INPUT)

TO

(OUTPUT)

VCC = 3.3 V

± 0.3 V

MIN MAX MIN MAX MIN TYP†MAX MIN MAX

1 4.2 4.7 1 2.7 4 4.5
1 4.1 5.1 1 2.9 3.9 4.9
1 4.9 6.2 1 3.4 4.7 6

1.1 4.9 6.7 1.1 3.4 4.7 6.5

1.8 5.3 5.9 1.8 3.7 5.1 5.7

1.3 4.7 4.2 1.3 2.6 4.5 4

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LVT125, SN74LVT125

3.3-V ABT QUADRUPLE BUS BUFFERS
WITH 3-STATE OUTPUTS

SCBS133D – MA Y 1992 – REVISED JULY 1995

PARAMETER MEASUREMENT INFORMATION

t

w

1.5 V

500 Ω

500 Ω

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT FOR OUTPUTS

Input

Output

Output

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

Input

t

PLH

t

PHL

INVERTING AND NONINVERTING OUTPUTS

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

t

1.5 V

t

PLH

1.5 V1.5 V

S1

PHL

2.7 V

0 V

V

OH

V

OL

V

OH

V

OL

6 V

Open

GND

2.7 V

0 V

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

TEST S1

1.5 V

Open

6 V

GND

t

h

1.5 V

VOL + 0.3 V

VOH – 0.3 V

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V

t

PZL

t

PLZ

1.5 V

t

t

PZH

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

PHZ

1.5 V

VOLTAGE WAVEFORMS

2.7 V

0 V

2.7 V

0 V

2.7 V

0 V

3 V

V

OL

V

OH

[

0 V

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

SN54LVT125, SN74LVT125

3.3-V ABT QUADRUPLE BUS BUFFERS
WITH 3-STATE OUTPUTS

SCBS133D – MA Y 1992 – REVISED JULY 1995

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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