SN74LVCZ245A
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES275B – JUNE 1999 – REVISED JANUARY 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
T ypical V
OLP
(Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D
T ypical V
OHV
(Output VOH Undershoot) >2 V
at V
CC
= 3.3 V, TA = 25°C
D
I
off
and Power-Up 3-State Support Hot
Insertion
D
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V VCC)
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
Package Options Include Shrink
Small-Outline (DB), Plastic Thin Very
Small-Outline (DGV), Small-Outline (DW),
and Thin Shrink Small-Outline (PW)
Packages
description
This octal bus transceiver is designed for 2.7-V to 3.6-V VCC operation.
The SN74L VCZ245A is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
When VCC is between 0 and 1.5 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN74LVCZ245A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
L L B data to A bus
L H A data to B bus
H X Isolation
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
DB, DGV, DW, OR PW PACKAGE
(TOP VIEW)
SN74LVCZ245A
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES275B – JUNE 1999 – REVISED JANUARY 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
B2
17
B3
16
B4
15
A5
6
A6
7
A7
8
A8
9
A2
3
A3
4
A4
5
OE
A1
2
G3
19
3 EN2 [AB]
B5
14
B6
13
B7
12
B8
11
B1
18
3 EN1 [BA]
1
DIR
1
2
logic diagram (positive logic)
DIR
OE
A1
B1
To Seven Other Channels
1
2
19
18