SN74LVCR162245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES047 - AUGUST 1995
D
Member of the Texas Instruments
Widebus
D
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Typical V
(Output Ground Bounce)
OLP
< 0.8 V at VCC = 3.3 V, TA = 25°C
D
Typical V
(Output VOH Undershoot)
OHV
> 2 V at VCC = 3.3 V, TA = 25°C
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JEDEC Standard JESD-17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
All Outputs Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
D
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 16-bit (dual-octal) noninverting bus
transceiver is designed for 2.7-V to 3.6-V V
operation.
CC
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
V
CC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
V
CC
2B5
2B6
GND
2B7
2B8
2DIR
1OE
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CC
2A5
2A6
GND
2A7
2A8
2OE
The SN74LVCR162245 is designed for asynchronous communication between data buses. The control
function implementation minimizes external timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the
A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR)
input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
All outputs, which are designed to sink up to 12 mA, include 26-Ω resistors to reduce overshoot and undershoot.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVCR162245 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are a trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1995, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN74LVCR162245
OPERATION
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES047 - AUGUST 1995
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE DIR
L L B data to A bus
L H A data to B bus
H X Isolation
logic symbol
48
1OE
2OE
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
1
25
24
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1DIR
2DIR
†
G3
3 EN1 [BA]
3 EN2 [AB]
G6
6 EN4 [BA]
6 EN5 [AB]
1
2
4
5
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
logic diagram (positive logic)
1
1DIR
47
1A1
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2DIR
2A1
24
36
To Seven Other Channels
48
25
13
1OE
2
1B1
2OE
2B1
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
2
To Seven Other Channels
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IOHHigh-level output current
mA
IOLLow-level output current
mA
SN74LVCR162245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES047 - AUGUST 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, VI: Except I/O ports (see Note 1) –0.5 V to VCC + 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 3):DGG package 0.85 W. . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Data Book
, literature number SCBD002B.
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
I/O ports (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .
(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
DL package 1.2 W. . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Package Thermal Considerations
application note in the 1994
ABT Advanced BiCMOS T echnology
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
CC
V
IH
V
IL
V
I
V
O
∆t/∆V Input transition rise or fall rate 0 10 ns/V
T
A
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
Supply voltage 2.7 3.6 V
High-level input voltage VCC = 2.7 V to 3.6 V 2 V
Low-level input voltage VCC = 2.7 V to 3.6 V 0.8 V
Input voltage 0 V
Output voltage 0 V
p
p
Operating free-air temperature –40 85 °C
VCC = 2.7 V –8
VCC = 3 V –12
VCC = 2.7 V 8
VCC = 3 V 12
CC
CC
V
V
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74LVCR162245
3 V
A
()
(INPUT)
(OUTPUT)
C
Power dissipation capacitance per transceiver
C
pF
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES047 - AUGUST 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS V
IOH = –100 µA MIN to MAX VCC–0.2
IOH = –4 mA, VIH = 2 V 2.7 V 2.2
V
OH
V
OL
I
l
I
l(hold)
§
I
OZ
I
CC
n
I
CC
C
C
†
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
‡
All typical values are at VCC = 3.3 V, TA = 25°C.
§
For I/O ports, the parameter IOZ includes the input leakage current.
Control inputs VI = VCC or GND 3.3 V 2.5 pF
i
A or B ports VO = VCC or GND 3.3 V 3.5 pF
io
IOH = –8 mA, VIH = 2 V 2.7 V 2
IOH = –6 mA, VIH = 2 V 3 V 2.4
IOH = –12 mA, VIH = 2 V 3 V 2
IOH = –100 µA MIN to MAX 0.2
IOH = –4 mA, VIL = 0.8 V 2.7 V 0.4
IOH = –8 mA, VIL = 0.8 V 2.7 V 0.6
IOH = –6 mA, VIL = 0.8 V 3 V 0.55
IOH = –12 mA, VIL = 0.8 V 3 V 0.8
VI = VCC or GND 3.6 V ±5 µA
VI = 0.8 V
VI = 2 V
VI = 0 to 3.6 V 3.6 V ±500 µA
VO = VCC or GND 3.6 V ±10 µA
VI = VCC or GND, IO = 0 3.6 V 20 µA
One input at VCC – 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V 500 µA
CC
†
MIN TYP‡MAX UNIT
V
V
75
–75
µ
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
t
pd
t
en
t
dis
operating characteristics, V
pd
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM
A or B B or A 1.5 7.5 1.5 8.5 ns
OE
OE
= 3.3 V, TA = 25
CC
PARAMETER TEST CONDITIONS TYP UNIT
p
p
p
_
C
Outputs enabled
Outputs enabled
TO
A or B 1.5 9 1.5 10 ns
A or B 1.5 7.5 1.5 8.5 ns
VCC = 3.3 V
± 0.3 V
MIN MAX MIN MAX
p
= 50 pF, f = 10 MHz
L
VCC = 2.7 V
20
2
UNIT
p
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 50 pF
(see Note A)
PARAMETER MEASUREMENT INFORMATION
6 V
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
500 Ω
500 Ω
S1
Open
GND
SN74LVCR162245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES047 - AUGUST 1995
TEST S1
Open
6 V
GND
LOAD CIRCUIT FOR OUTPUTS
t
w
Input
Output
Output
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
Input
t
PLH
t
PHL
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V 1.5 V
1.5 V
VOLTAGE WAVEFORMS
t
PHL
1.5 V
t
PLH
1.5 V1.5 V
2.7 V
0 V
V
OH
V
OL
V
OH
V
OL
2.7 V
0 V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PLZ
1.5 V
t
t
PZH
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
VOLTAGE WAVEFORMS
t
h
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
[
0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PHL
and t
and t
and t
are the same as t
PHZ
are the same as t
PZH
are the same as tpd.
PLH
dis
den
.
Figure 1. Load Circuit and Voltage Waveforms
.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
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Copyright 1998, Texas Instruments Incorporated
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