Texas Instruments SN74LVCH32244AGKER Datasheet
SN74LVCH32244A
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS617A – OCTOBER 1998 – REVISED JUNE 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
T ypical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, TA = 25°C
D
T ypical V
OHV
(Output VOH Undershoot)
> 2 V at V
CC
= 3.3 V, TA = 25°C
D
I
off
Supports Partial-Power-Down-Mode
Operation
D
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V
CC
)
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
Packaged in Plastic Fine-Pitch Ball Grid
Array Package
description
This 32-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVCH32244A is designed specifically to improve the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented receivers and transmitters.
The device can be used as eight 4-bit buffers, four 8-bit buffers, two 16-bit buffers, or one 32-bit buffer . It provides
true outputs and symmetrical active-low output-enable (OE
) inputs.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVCH32244A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OUTPUT
OE
A
Y
L H H
L LL
HXZ
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
SN74LVCH32244A
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS617A – OCTOBER 1998 – REVISED JUNE 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GKE PACKAGE
(TOP VIEW)
JHGFEDCBA
2
1
3
4
6
5
PNMLK TR
terminal assignments
6 1A2 1A4 2A2 2A4 3A2 3A4 4A2 4A3 5A2 5A4 6A2 6A4 7A2 7A4 8A2 8A3
5 1A1 1A3 2A1 2A3 3A1 3A3 4A1 4A4 5A1 5A3 6A1 6A3 7A1 7A3 8A1 8A4
4 2OE GND V
CC
GND GND V
CC
GND 3OE 6OE GND V
CC
GND GND V
CC
GND 7OE
3 1OE GND V
CC
GND GND V
CC
GND 4OE 5OE GND V
CC
GND GND V
CC
GND 8OE
2 1Y1 1Y3 2Y1 2Y3 3Y1 3Y3 4Y1 4Y4 5Y1 5Y3 6Y1 6Y3 7Y1 7Y3 8Y1 8Y4
1 1Y2 1Y4 2Y2 2Y4 3Y2 3Y4 4Y2 4Y3 5Y2 5Y4 6Y2 6Y4 7Y2 7Y4 8Y2 8Y3
A B C D E F G H J K L M N P R T
SN74LVCH32244A
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS617A – OCTOBER 1998 – REVISED JUNE 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1OE
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
A3
A5
A6
B5
B6
A2
A1
B2
B1
2OE
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
A4
C5
C6
D5
D6
C2
C1
D2
D1
3OE
3A1
3A2
3A3
3A4
3Y1
3Y2
3Y3
3Y4
H4
E5
E6
F5
F6
E2
E1
F2
F1
4OE
4A1
4A2
4A3
4A4
4Y1
4Y2
4Y3
4Y4
H3
G5
G6
H6
H5
G2
G1
H1
H2
5OE
5A1
5A2
5A3
5A4
5Y1
5Y2
5Y3
5Y4
J3
J5
J6
K5
K6
J2
J1
K2
K1
6OE
6A1
6A2
6A3
6A4
6Y1
6Y2
6Y3
6Y4
J4
L5
L6
M5
M6
L2
L1
M2
M1
7OE
7A1
7A2
7A3
7A4
7Y1
7Y2
7Y3
7Y4
T4
N5
N6
P5
P6
N2
N1
P2
P1
8OE
8A1
8A2
8A3
8A4
8Y1
8Y2
8Y3
8Y4
T3
R5
R6
T6
T5
R2
R1
T1
T2
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