Datasheet SN74LVCH244ADBLE, SN74LVCH244ADBR, SN74LVCH244ADGVR, SN74LVCH244ADW, SN74LVCH244ADWR Datasheet (Texas Instruments)
...
SN54LVCH244A, SN74LVCH244A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES009G – JULY 1995 - REVISED JUNE 1998
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Typical V
< 0.8 V at V
D
Typical V
> 2 V at V
D
Power Off Disables Outputs, Permitting
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
(Output VOH Undershoot)
OHV
= 3.3 V, TA = 25°C
CC
Live Insertion
D
Support Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V
D
ESD Protection Exceeds 2000 V Per
CC
)
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Flat (W) Package,
Ceramic Chip Carriers (FK), and DIPs (J)
SN54LVCH244A...J OR W PACKAGE
SN74LVCH244A. . . DB, DW, OR PW PACKAGE
SN54LVCH244A. . . FK PACKAGE
1A2
2Y3
1A3
2Y2
1A4
(TOP VIEW)
1OE
1
1A1
2
2Y4
3
1A2
4
2Y3
5
1A3
6
2Y2
7
1A4
8
9
2Y1
GND
10
(TOP VIEW)
2Y4
3212019
4
5
6
7
8
910111213
1A1
20
19
18
17
16
15
14
13
12
11
1OE
V
CC
V
CC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
18
17
16
15
14
1Y1
2A4
1Y2
2A3
1Y3
description
2Y1
GND
2A1
1Y4
2A2 2OE
The SN54LVCH244A octal buffer/line driver is designed for 2.7-V to 3.6-V VCC operation and the
SN74LVCH244A octal buffer/line driver is designed for 1.65-V to 3.6-V V
These devices are organized as two 4-bit line drivers with separate output-enable (OE
these devices pass data from the A inputs to the Y outputs. When OE
operation.
CC
) inputs. When OE is low,
is high, the outputs are in the
high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54L VCH244A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVCH244A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54LVCH244A, SN74LVCH244A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES009G – JULY 1995 - REVISED JUNE 1998
FUNCTION TABLE
(each buffer)
INPUTS
OE A
L H H
L LL
HXZ
OUTPUT
Y
logic symbol
1OE
1A1
1A2
1A3
1A4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
1
2
4
6
8
EN
18
16
14
12
1Y1
1Y2
1Y3
1Y4
2OE
2A1
2A2
2A3
2A4
logic diagram (positive logic)
1
1OE
218
1A1
416
1A2
1Y1
1Y2
2OE
2A1
2A2
19
11
13
15
17
19
11 9
13 7
EN
2Y1
2Y2
9
2Y1
7
2Y2
5
2Y3
3
2Y4
614
1A3
812
1A4
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1Y3
1Y4
15 5
2A3
17 3
2A4
2Y3
2Y4
UNIT
VCCSuppl
oltage
V
VOOutput voltage
V
IOHHigh-level output current
mA
IOLLow-level output current
mA
SN54LVCH244A, SN74LVCH244A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES009G – JULY 1995 - REVISED JUNE 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in the high-impedance or power-off state, V
–0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
O
†
(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 4)
SN54LVCH244A SN74LVCH244A
MIN MAX MIN MAX
pp
y v
V
V
V
∆t/∆v Input transition rise or fall rate 0 10 0 10 ns/V
T
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 5.5 0 5.5 V
I
p
p
p
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
Operating 2 3.6 1.65 3.6
Data retention only 1.5 1.5
VCC = 1.65 V to 1.95 V 0.65 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 2 2
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 0.8 0.8
High or low state 0 V
3 state 0 5.5 0 5.5
VCC = 1.65 V –4
VCC = 2.3 V –8
VCC = 2.7 V –12 –12
VCC = 3 V –24 –24
VCC = 1.65 V 4
VCC = 2.3 V 8
VCC = 2.7 V 12 12
VCC = 3 V 24 24
, literature number SCBA004.
CC
CC
1.7
0 V
0.7
CC
V
CC
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54LVCH244A, SN74LVCH244A
PARAMETER
TEST CONDITIONS
V
UNIT
I
100 µA
I
mA
I
100 µA
V
V
1.65 V
I
A
2.3 V
3 V
()
I
I
0
3.6 V
A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES009G – JULY 1995 - REVISED JUNE 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
= –
OH
IOH = –4 mA 1.65 V 1.2
V
OH
OL
I
I
I
off
I(hold)
I
I(hold)
I
OZ
CC
∆I
CC
C
i
C
†
‡
§
¶
o
All typical values are at VCC = 3.3 V, TA = 25°C.
This information was not available at the time of publication.
This is the bus-hold maximum dynamic current required to switch the input from one state to another.
This applies in the disabled state only.
IOH = –8 mA 2.3 V 1.7
= –12
OH
IOH = –24 mA 3 V 2.2 2.2
=
OL
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.7
IOL = 12 mA 2.7 V 0.4 0.4
IOL = 24 mA 3 V 0.55 0.55
VI = 0 to 5.5 V 3.6 V ±5 ±5 µA
VI or VO = 5.5 V 0 ±10 µA
VI = 0.58 V
VI = 1.07 V
VI = 0.7 V
VI = 1.7 V
VI = 0.8 V
VI = 2 V
VI = 0 to 3.6 V
VO = 0 to 5.5 V 3.6 V ±15 ±10 µA
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V
One input at VCC – 0.6 V,
Other inputs at VCC or GND
VI = VCC or GND 3.3 V 4 12 4 pF
VO = VCC or GND 3.3 V 5.5 12 5.5 pF
§
=
O
¶
1.65 V to 3.6 V VCC–0.2
2.7 V to 3.6 V VCC–0.2
2.7 V 2.2 2.2
3 V 2.4 2.4
1.65 V to 3.6 V 0.2
2.7 V to 3.6 V 0.2
3..6 V ±500 ±500
2.7 V to 3.6 V 500 500 µA
SN54LVCH244A SN74LVCH244A
MIN TYP†MAX MIN TYP†MAX
‡
‡
45
–45
75 75
–75 –75
10 10
10 10
V
µ
µA
µ
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CONDITIONS
C
d
f
pF
SN54LVCH244A, SN74LVCH244A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES009G – JULY 1995 - REVISED JUNE 1998
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
SN54LVCH244A
PARAMETER
t
pd
t
en
t
dis
FROM
(INPUT)
A Y 7.5 1 6.5 ns
OE
OE
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
t
pd
t
en
t
dis
†
This information was not available at the time of publication.
FROM
(INPUT)
A Y
OE
OE
TO
(OUTPUT)
Y
Y
VCC = 1.8 V
± 0.15 V
MIN MAX MIN MAX MIN MAX MIN MAX
† † † †
† † † †
† † † †
TO
(OUTPUT)
Y 9 1 8 ns
Y 8 1 7 ns
SN74LVCH244A
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
MIN MAX MIN MAX
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
VCC = 3.3 V
± 0.3 V
6.9 1.5 5.9 ns
8.6 1 7.6 ns
6.8 1.5 5.8 ns
UNIT
UNIT
operating characteristics, T
PARAMETER
Power dissipation capacitance
p
per buffer/driver
†
This information was not available at the time of publication.
= 25°C
A
Outputs enabled
Outputs disabled
TEST
= 10 MHz
VCC = 1.8 V
± 0.15 V
TYP TYP TYP
† †
† †
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
47
2
UNIT
p
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54LVCH244A, SN74LVCH244A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES009G – JULY 1995 - REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 30 pF
(see Note A)
1k Ω
1k Ω
S1
= 1.8 V ± 0.15 V
V
CC
2 × V
CC
Open
GND
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
Open
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO = 50 Ω, tr≤2 ns, tf≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 30 pF
(see Note A)
SN54LVCH244A, SN74LVCH244A
OCTAL BUFFERS/DRIVERS
SCES009G – JULY 1995 - REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
V
= 2.5 V ± 0.2 V
CC
2 × V
500 Ω
500 Ω
S1
Open
GND
CC
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
WITH 3-STATE OUTPUTS
Open
2 × V
CC
GND
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO = 50 Ω, tr≤2 ns, tf≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN54LVCH244A, SN74LVCH244A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES009G – JULY 1995 - REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
= 2.7 V AND 3.3 V ± 0.3 V
V
CC
From Output
Under Test
CL = 50 pF
(see Note A)
Timing
Input
Data
Input
Input
t
PLH
Output
500 Ω
500 Ω
LOAD CIRCUIT
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
h
S1
t
PHL
6 V
GND
2.7 V
2.7 V
V
V
Open
0 V
0 V
2.7 V
0 V
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
t
w
t
1.5 V
t
1.5 V
Open
6 V
GND
1.5 V1.5 V
PLZ
PHZ
VOL + 0.3 V
VOH – 0.3 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO = 50 Ω, tr≤2.5 ns, tf≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
Figure 3. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
.
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