Texas Instruments SN74LVCH16652ADL, SN74LVCH16652ADLR, SN74LVCH16652ADGVR Datasheet

SN74LVCH16652A

16-BIT BUS TRANSCEIVER AND REGISTER

WITH 3-STATE OUTPUTS

SCAS319G – NOVEMBER 1993 – REVISED JUNE 1998

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Member of the Texas Instruments

Widebus

 Family

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

T ypical V

OLP

(Output Ground Bounce)

< 0.8 V at V

CC

= 3.3 V, TA = 25°C

D

T ypical V

OHV

(Output VOH Undershoot)

> 2 V at V

CC

= 3.3 V, TA = 25°C

D

Power Off Disables Outputs, Permitting
Live Insertion

D

Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With

3.3-V V

CC

)

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages

description

This 16-bit bus transceiver and register is
designed for 1.65-V to 3.6-V V

CC

operation.

The SN74LVCH16652A consists of D-type
flip-flops and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
The device can be used as two 8-bit transceivers
or one 16-bit transceiver.

Complementary output-enable (OEAB and OEBA

) inputs control the transceiver functions. Select-control (SAB
and SBA) inputs select whether real-time or stored data is transferred. A low input level selects real-time data,
and a high input level selects stored data. The circuitry used for select control eliminates the typical decoding
glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates
the four fundamental bus-management functions that can be performed with the SN74LVCH16652A.

Copyright  1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

DGG OR DL PACKAGE

(TOP VIEW)

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1OEAB

1CLKAB

1SAB

GND

1A1
1A2

V

CC

1A3
1A4
1A5

GND

1A6
1A7
1A8
2A1
2A2
2A3

GND

2A4
2A5
2A6

V

CC

2A7
2A8

GND

2SAB

2CLKAB

2OEAB

1OEBA
1CLKBA
1SBA
GND
1B1
1B2
V

CC

1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V

CC

2B7
2B8
GND
2SBA
2CLKBA
2OEBA

SN74LVCH16652A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS

SCAS319G – NOVEMBER 1993 – REVISED JUNE 1998

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs regardless of the levels on the select-control or output-enable
inputs. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the
internal D-type flip-flops by simultaneously enabling OEAB and OEBA

. In this configuration, each output
reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set
of bus lines remains at its last level configuration.

To ensure the high-impedance state during power up or power down, OEBA

should be tied to VCC through a
pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor
is determined by the current-sinking/current-sourcing capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.

Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.
The SN74LVCH16652A is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

DATA I/O

†

OEAB

OEBA

CLKAB CLKBA SAB SBA A1–A8 B1–B8

OPERATION OR FUNCTION

L H H or L H or L X X Input Input Isolation
L H ↑↑X X Input Input Store A and B data
X H ↑ H or L X X Input Unspecified

‡

Store A, hold B

H H ↑↑X

‡

X Input Output Store A in both registers

L X H or L ↑ X X Unspecified

‡

Input Hold A, store B

L L ↑↑XX

‡

Output Input Store B in both registers
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
H H X X L X Input Output Real-time A data to B bus
H H H or L X H X Input Output Stored A data to B bus

H L H or L H or L H H Output Output

Stored A data to B bus and

stored B data to A bus

†

The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA

. Data-input functions always are

enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.

‡

Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.

SN74LVCH16652A

16-BIT BUS TRANSCEIVER AND REGISTER

WITH 3-STATE OUTPUTS

SCAS319G – NOVEMBER 1993 – REVISED JUNE 1998

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

REAL-TIME TRANSFER

BUS B TO BUS A

REAL-TIME TRANSFER

BUS A TO BUS B

STORAGE FROM

A, B, OR A AND B

TRANSFER STORED DATA

TO A AND/OR B

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

OEAB

X
L
L

OEAB

LL

CLKABXCLKBAXSABXSBA

L

CLKABXCLKBAXSABLSBA

X

H

CLKAB CLKBAXSABXSBA

X

CLKAB CLKBA SAB SBA

X
H

XX

X

X
X

H L H or L H H

↑

↑
↑↑

OEBA

OEBA

HH

OEAB OEBA

OEAB OEBA

H or L

Figure 1. Bus-Management Functions

SN74LVCH16652A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS

SCAS319G – NOVEMBER 1993 – REVISED JUNE 1998

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

C3

EN7 [BA]

29

G12

26

2SAB

5

1A1

1A2

6

1A3

8

1A4

9

1A5

10

1A6

12

1A7

13

1A8

14

1B6

45

1B7

44

1B8

43

1B2

51

1B3

49

1B4

48

1B5

47

1B1

52

3D

27

2CLKAB

G10

31

2SBA

30

2CLKBA

EN8 [AB]

28

2OEAB

EN1 [BA]

56

G6

3

1SAB

2

1CLKAB

G4

54

1SBA

55

1CLKBA

EN2 [AB]

1

1OEAB

C5

C9

C11

15

2A1

2A2

16

2A3

17

2A4

19

2A5

20

2A6

21

2A7

23

2A8

24

2B6

36

2B7

34

2B8

33

2B2

41

2B3

40

2B4

38

2B5

37

2B1

42

9D

1OEBA

2OEBA

5D

1

≥ 1

≥ 1

2

16

6

4

4

1

11D

7

≥ 1

≥ 1

8

112

12

10

10

1

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.