Texas Instruments SN74LVCH16543ADGGR, SN74LVCH16543ADGVR, SN74LVCH16543ADL, SN74LVCH16543ADLR Datasheet
SN74LVCH16543A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS317F – NOVEMBER 1993 – REVISED JUNE 1998
D
Member of the Texas Instruments
D
Widebus
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Typical V
< 0.8 V at V
D
Typical V
> 2 V at V
D
Power Off Disables Outputs, Permitting
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
(Output VOH Undershoot)
OHV
= 3.3 V, TA = 25°C
CC
Live Insertion
D
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V
D
ESD Protection Exceeds 2000 V Per
CC
)
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 16-bit registered transceiver is designed for
1.65-V to 3.6-V V
The SN74L VCH16543A can be used as two 8-bit
transceivers or one 16-bit transceiver. Separate
latch-enable (LEAB
(OEAB
or OEBA) inputs are provided for each
register to permit independent control in either
direction of data flow.
operation.
CC
or LEBA) and output-enable
DGG OR DL PACKAGE
(TOP VIEW)
1OEAB
1LEAB
1CEAB
GND
GND
GND
GND
2CEAB
2LEAB
2OEAB
1A1
1A2
V
CC
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
V
CC
2A7
2A8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEBA
1LEBA
1CEBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2CEBA
2LEBA
2OEBA
The A-to-B enable (CEAB
LEAB
is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches
in the storage mode. With CEAB
) input must be low to enter data from A or to output data from B. If CEAB is low and
and OEAB both low, the 3-state B outputs are active and reflect the data
present at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA
OEBA
inputs.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
, LEBA, and
1
SN74LVCH16543A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS317F – NOVEMBER 1993 – REVISED JUNE 1998
description (continued)
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVCH16543A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 8-bit section)
INPUTS
CEAB LEAB OEAB A
H X X X Z
X XHX Z
LHLXB
LLLL L
LLLHH
†
A-to-B data flow is shown; B-to-A flow control is the
same except that it uses CEBA
‡
Output level before the indicated steady-state input
conditions were established
†
OUTPUT
B
‡
0
, LEBA, and OEBA.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH16543A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS317F – NOVEMBER 1993 – REVISED JUNE 1998
logic symbol
†
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
56
54
55
1
3
2
29
31
30
28
26
27
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
1EN3
G1
1C5
2EN4
G2
2C6
7EN9
G7
7C11
8EN10
G8
8C12
3
6D
9
12D
5D
4
11D
10
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74LVCH16543A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS317F – NOVEMBER 1993 – REVISED JUNE 1998
logic diagram (positive logic)
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
1A1
2OEBA
56
54
55
1
3
2
5
29
C1
1D
To Seven Other Channels
C1
1D
52
1B1
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
2A1
31
30
28
26
27
15
C1
1D
To Seven Other Channels
C1
1D
42
2B1
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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