Texas Instruments SN74LVCH16543ADGGR, SN74LVCH16543ADGVR, SN74LVCH16543ADL, SN74LVCH16543ADLR Datasheet
SN74LVCH16543A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS317F – NOVEMBER 1993 – REVISED JUNE 1998
D
Member of the Texas Instruments
D
Widebus
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Typical V
< 0.8 V at V
D
Typical V
> 2 V at V
D
Power Off Disables Outputs, Permitting
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
(Output VOH Undershoot)
OHV
= 3.3 V, TA = 25°C
CC
Live Insertion
D
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V
D
ESD Protection Exceeds 2000 V Per
CC
)
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 16-bit registered transceiver is designed for
1.65-V to 3.6-V V
The SN74L VCH16543A can be used as two 8-bit
transceivers or one 16-bit transceiver. Separate
latch-enable (LEAB
(OEAB
or OEBA) inputs are provided for each
register to permit independent control in either
direction of data flow.
operation.
CC
or LEBA) and output-enable
DGG OR DL PACKAGE
(TOP VIEW)
1OEAB
1LEAB
1CEAB
GND
GND
GND
GND
2CEAB
2LEAB
2OEAB
1A1
1A2
V
CC
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
V
CC
2A7
2A8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEBA
1LEBA
1CEBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2CEBA
2LEBA
2OEBA
The A-to-B enable (CEAB
LEAB
is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches
in the storage mode. With CEAB
) input must be low to enter data from A or to output data from B. If CEAB is low and
and OEAB both low, the 3-state B outputs are active and reflect the data
present at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA
OEBA
inputs.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
, LEBA, and
1
SN74LVCH16543A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS317F – NOVEMBER 1993 – REVISED JUNE 1998
description (continued)
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVCH16543A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 8-bit section)
INPUTS
CEAB LEAB OEAB A
H X X X Z
X XHX Z
LHLXB
LLLL L
LLLHH
†
A-to-B data flow is shown; B-to-A flow control is the
same except that it uses CEBA
‡
Output level before the indicated steady-state input
conditions were established
†
OUTPUT
B
‡
0
, LEBA, and OEBA.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH16543A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS317F – NOVEMBER 1993 – REVISED JUNE 1998
logic symbol
†
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
56
54
55
1
3
2
29
31
30
28
26
27
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
1EN3
G1
1C5
2EN4
G2
2C6
7EN9
G7
7C11
8EN10
G8
8C12
3
6D
9
12D
5D
4
11D
10
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74LVCH16543A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS317F – NOVEMBER 1993 – REVISED JUNE 1998
logic diagram (positive logic)
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
1A1
2OEBA
56
54
55
1
3
2
5
29
C1
1D
To Seven Other Channels
C1
1D
52
1B1
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
2A1
31
30
28
26
27
15
C1
1D
To Seven Other Channels
C1
1D
42
2B1
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VCCSuppl
oltage
V
VOOutput voltage
V
IOHHigh-level output current
mA
IOLLow-level output current
mA
SN74LVCH16543A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS317F – NOVEMBER 1993 – REVISED JUNE 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in the high-impedance or power-off state, V
–0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
:(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
O
†
(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through each V
Package thermal impedance, θ
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
JA
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 4)
MIN MAX UNIT
pp
y v
V
V
V
∆t/∆v Input transition rise or fall rate 0 10 ns/V
T
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 5.5 V
I
p
p
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
Operating 1.65 3.6
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × V
VCC = 2.3 V to 2.7 V 1.7
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 0.8
High or low state 0 V
3 state 0 5.5
VCC = 1.65 V –4
VCC = 2.3 V –8
VCC = 2.7 V –12
VCC = 3 V –24
VCC = 1.65 V 4
VCC = 2.3 V 8
VCC = 2.7 V 12
VCC = 3 V 24
CC
0.7
CC
V
CC
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74LVCH16543A
V
V
I
mA
1.65 V
2.3 V
()
3 V
I
I
0
3.6 V
A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS317F – NOVEMBER 1993 – REVISED JUNE 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
IOH = –100 µA 1.65 V to 3.6 V VCC–0.2
IOH = –4 mA 1.65 V 1.2
OH
V
OL
I
I
I
off
I
I(hold)
I
OZ
CC
∆I
C
C
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
This information was not available at the time of publication.
§
This is the bus-hold maximum dynamic current required to switch the input from one state to another.
¶
For I/O ports, the parameter IOZ includes the input leakage current, but not I
#
This applies in the disabled state only.
Control inputs VI = 0 to 5.5 V 3.6 V ±5 µA
A or B ports
¶
CC
Control inputs VI = VCC or GND 3.3 V 5 pF
i
A or B ports VO = VCC or GND 3.3 V 8 pF
io
IOH = –8 mA 2.3 V 1.7
= –12
OH
IOH = –24 mA 3 V 2.2
IOL = 100 µA 1.65 V to 3.6 V 0.2
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.7
IOL = 12 mA 2.7 V 0.4
IOL = 24 mA 3 V 0.55
VI or VO = 5.5 V 0 ±10 µA
VI = 0.58 V
VI = 1.07 V
VI = 0.7 V
VI = 1.7 V
VI = 0.8 V
VI = 2 V
VI = 0 to 3.6 V
VO = 0 to 5.5 V 3.6 V ±10 µA
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V
One input at VCC – 0.6 V,
Other inputs at
VCC or GND
§
=
O
#
.
I(hold)
V
CC
2.7 V 2.2
3 V 2.4
3..6 V ±500
2.7 V to 3.6 V 500 µA
MIN TYP†MAX UNIT
V
‡
‡
45
20
20
µA
µ
–45
75
–75
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
t
w
t
su
t
h
‡
This information was not available at the time of publication.
6
Pulse duration, LE or CE low ‡ ‡ 3.3 3.3 ns
Setup time, data before LE or CE↓ ‡ ‡ 1.1 1.1 ns
Hold time, data after LE or CE↓ ‡ ‡ 1.9 1.9 ns
VCC = 1.8 V
± 0.15 V
MIN MAX MIN MAX MIN MAX MIN MAX
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
(INPUT)
(OUTPUT)
t
ns
CE
A or B
ns
OE
A or B
ns
CONDITIONS
C
d
f
pF
SN74LVCH16543A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS317F – NOVEMBER 1993 – REVISED JUNE 1998
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
pd
t
en
t
dis
t
en
t
dis
†
This information was not available at the time of publication.
operating characteristics, T
Power dissipation capacitance
p
per transceiver
†
This information was not available at the time of publication.
FROM
A or B B or A † † † † 6.1 1.2 5.4
LE A or B † † † † 7.4 1.5 6.1
A
PARAMETER
TO
= 25°C
Outputs enabled
Outputs disabled
VCC = 1.8 V
± 0.15 V
MIN MAX MIN MAX MIN MAX MIN MAX
† † † † 7.9 1.2 6.6
† † † † 7.1 1.5 6.6
† † † † 7.6 1 6.3
† † † † 6.9 1.5 6.3
TEST
= 10 MHz
VCC = 2.5 V
± 0.2 V
VCC = 1.8 V
± 0.15 V
VCC = 2.7 V
VCC = 2.5 V
± 0.2 V
TYP TYP TYP
† † 44
† † 4
VCC = 3.3 V
± 0.3 V
VCC = 3.3 V
± 0.3 V
UNIT
UNIT
p
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN74LVCH16543A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS317F – NOVEMBER 1993 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 30 pF
(see Note A)
1k Ω
1k Ω
S1
V
= 1.8 V ± 0.15 V
CC
2 × V
CC
Open
GND
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
Open
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 30 pF
(see Note A)
16-BIT REGISTERED TRANSCEIVER
SCAS317F – NOVEMBER 1993 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
V
= 2.5 V ± 0.2 V
CC
2 × V
500 Ω
500 Ω
S1
Open
GND
CC
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
SN74LVCH16543A
WITH 3-STATE OUTPUTS
Open
2 × V
CC
GND
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
SN74LVCH16543A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS317F – NOVEMBER 1993 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.7 V AND 3.3 V ± 0.3 V
From Output
Under Test
CL = 50 pF
(see Note A)
Timing
Input
Data
Input
Input
t
PLH
Output
500 Ω
500 Ω
LOAD CIRCUIT
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
h
S1
t
PHL
6 V
GND
Open
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
V
OH
V
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
t
w
t
PLZ
1.5 V
t
PHZ
1.5 V
Open
6 V
GND
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
Figure 3. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
.
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 1998, Texas Instruments Incorporated
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