Texas Instruments SN74LVCH16540ADGGR, SN74LVCH16540ADGVR, SN74LVCH16540ADL, SN74LVCH16540ADLR Datasheet

SN74LVCH16540A

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

SCAS569G – MARCH 1996 – REVISED JUNE 1998

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Member of the Texas Instruments

Widebus

 Family

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

T ypical V

OLP

(Output Ground Bounce)

< 0.8 V at VCC = 3.3 V, TA = 25°C

D

T ypical V

OHV

(Output VOH Undershoot)

> 2 V at VCC = 3.3 V, TA = 25°C

D

Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With

3.3-V V

CC

)

D

Power Off Disables Outputs, Permitting
Live Insertion

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin-Shrink
Small-Outline (DGG) Packages

description

This 16-bit buffer/driver is designed for 1.65-V to

3.6-V VCC operation, and provides a
high-performance bus interface for wide data
paths.

The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2)
input is high, all corresponding outputs are in the high-impedance state.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.

T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVCH16540A is characterized for operation from –40°C to 85°C.

Copyright  1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

DGG OR DL PACKAGE

(TOP VIEW)

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1OE1

1Y1
1Y2

GND

1Y3
1Y4

V

CC

1Y5
1Y6

GND

1Y7
1Y8
2Y1
2Y2

GND

2Y3
2Y4

V

CC

2Y5
2Y6

GND

2Y7
2Y8

2OE1

1OE2
1A1
1A2
GND
1A3
1A4
V

CC

1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V

CC

2A5
2A6
GND
2A7
2A8
2OE2

SN74LVCH16540A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS

SCAS569G – MARCH 1996 – REVISED JUNE 1998

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

(each 8-bit section)

INPUTS

OUTPUT

OE1 OE2

A

Y

L L L H
L LH L
H XX Z
X H X Z

logic symbol

†

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

47

1A1

1

1Y1

2

48

46

1A2 1Y2

3

24
25

44

1A3 1Y3

5

43

1A4

1Y4

6

41

1A5 1Y5

8

40

1A6 1Y6

9

38

1A7 1Y7

11

37

1A8 1Y8

12

36

2A1 2Y1

13

35

2A2 2Y2

14

33

2A3

2Y3

16

32

2A4 2Y4

17

30

2A5 2Y5

19

29

2A6 2Y6

20

27

2A7 2Y7

22

26

2A8 2Y8

23

1OE1
1OE2
2OE1
2OE2

&

&

11

12

EN1

EN2

logic diagram (positive logic)

1OE1
1OE2

2OE1
2OE2

1A1 1Y1

2Y1

2A1

To Seven Other Channels To Seven Other Channels

1
48

47

24
25

36

2

13

SN74LVCH16540A

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

SCAS569G – MARCH 1996 – REVISED JUNE 1998

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

–0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high-impedance or power-off state, V

O

(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or low state, V

O

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0 ) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 3): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The value of VCC is provided in the recommended operating conditions table.

3. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 4)

MIN MAX UNIT

pp

Operating 1.65 3.6

VCCSuppl

y v

oltage

Data retention only 1.5

V

VCC = 1.65 V to 1.95 V 0.65 × V

CC

V

IH

High-level input voltage

VCC = 2.3 V to 2.7 V

1.7

V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V

CC

V

IL

Low-level input voltage

VCC = 2.3 V to 2.7 V

0.7

V
VCC = 2.7 V to 3.6 V 0.8

V

I

Input voltage 0 5.5 V

p

High or low state 0 V

CC

VOOutput voltage

3 state 0 5.5

V

VCC = 1.65 V –4

p

VCC = 2.3 V –8

IOHHigh-level output current

VCC = 2.7 V –12

mA

VCC = 3 V –24
VCC = 1.65 V 4

p

VCC = 2.3 V 8

IOLLow-level output current

VCC = 2.7 V 12

mA

VCC = 3 V 24

∆t/∆v Input transition rise or fall rate 0 10 ns/V
T

A

Operating free-air temperature –40 85 °C

NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.