Datasheet SN74LVCH16374ADGGR, SN74LVCH16374ADGVR, SN74LVCH16374ADL, SN74LVCH16374ADLR Datasheet (Texas Instruments)
SN74LVCH16374A
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS565F – MARCH 1996 – REVISED JUNE 1998
D
Member of the Texas Instruments
D
Widebus
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Typical V
(Output Ground Bounce)
OLP
< 0.8 V at VCC = 3.3 V, TA = 25°C
D
Typical V
(Output VOH Undershoot)
OHV
> 2 V at VCC = 3.3 V, TA = 25°C
D
Power Off Disables Outputs, Permitting
Live Insertion
D
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input and Output Voltages
With 3.3-V VCC)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 16-bit edge-triggered D-type flip-flop is
designed for 1.65-V to 3.6-V VCC operation.
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1CLK
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2CLK
The SN74L VCH16374A is particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers. It
can be used as two 8-bit flip-flops or one 16-bit
flip-flop. On the positive transition of the clock
(CLK) input, the Q outputs of the flip-flop take on
the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly . The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE
does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
1
SN74LVCH16374A
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS565F – MARCH 1996 – REVISED JUNE 1998
description (continued)
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVCH16374A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLK D
OE
L ↑ H H
L ↑ LL
L H or L X Q
H X X Z
OUTPUT
Q
0
logic symbol
†
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1EN
2EN
1D
2D
C1
C2
11
12
13
14
16
17
19
20
22
23
2
1Q1
3
1Q2
5
1Q3
6
1Q4
8
1Q5
9
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
1
2
1OE
1CLK
2OE
2CLK
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
SN74LVCH16374A
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS565F – MARCH 1996 – REVISED JUNE 1998
1OE
1CLK
1D1
1
48
47
C1
1D
To Seven Other Channels
2CLK
1Q1
2OE
2D1
24
25
36
C1
1D
To Seven Other Channels
132
2Q1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, V
(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 3): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
O
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74LVCH16374A
VCCSuppl
oltage
V
VOOutput voltage
V
IOHHigh-level output current
mA
IOLLow-level output current
mA
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS565F – MARCH 1996 – REVISED JUNE 1998
recommended operating conditions (see Note 4)
MIN MAX UNIT
pp
y v
V
V
V
∆t/∆v Input transition rise or fall rate 0 10 ns/V
T
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 5.5 V
I
p
p
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
Operating 1.65 3.6
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 0.8
High or low state 0 V
3 state 0 5.5
VCC = 1.65 V –4
VCC = 2.3 V –8
VCC = 2.7 V –12
VCC = 3 V –24
VCC = 1.65 V 4
VCC = 2.3 V 8
VCC = 2.7 V 12
VCC = 3 V 24
CC
1.7
0.7
CC
V
CC
V
4
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V
V
I
mA
1.65 V
2.3 V
()
3 V
I
I
0
3.6 V
A
SN74LVCH16374A
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS565F – MARCH 1996 – REVISED JUNE 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
IOH = –100 µA 1.65 V to 3.6 V VCC–0.2
IOH = –4 mA 1.65 V 1.2
OH
V
OL
I
I
I
I(hold)
I
off
I
OZ
CC
∆I
CC
C
i
C
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
This information was not available at the time of publication.
§
This is the bus-hold maximum dynamic current required to switch the input from one state to another.
¶
This applies in the disabled state only.
o
IOH = –8 mA 2.3 V 1.7
= –12
OH
IOH = –24 mA 3 V 2.2
IOL = 100 µA 1.65 V to 3.6 V 0.2
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.7
IOL = 12 mA 2.7 V 0.4
IOL = 24 mA 3 V 0.55
VI = 0 to 5.5 V 3.6 V ±5 µA
VI = 0.58 V
VI = 1.07 V
VI = 0.7 V
VI = 1.7 V
VI = 0.8 V
VI = 2 V
VI = 0 to 3.6 V
VI or VO = 5.5 V 0 ±10 µA
VO = 0 to 5.5 V 3.6 V ±10 µA
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V
One input at VCC – 0.6 V,
Other inputs at VCC or GND
VI = VCC or GND 3.3 V 5 pF
VO = VCC or GND 3.3 V 6.5 pF
§
=
¶
O
V
2.7 V 2.2
3.6 V ±500
2.7 V to 3.6 V 500 µA
CC
3 V 2.4
MIN TYP†MAX UNIT
45
–45
75
–75
V
‡
‡
µA
20
µ
20
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
VCC = 1.8 V
± 0.15 V
MIN MAX MIN MAX MIN MAX MIN MAX
f
clock
t
w
t
su
t
h
‡
This information was not available at the time of publication.
Clock frequency ‡ ‡ 150 150 MHz
Pulse duration, CLK high or low ‡ ‡ 3.3 3.3 ns
Setup time, data before CLK↑ ‡ ‡ 1.9 1.9 ns
Hold time, data after CLK↑ ‡ ‡ 1.1 1.1 ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
5
SN74LVCH16374A
(INPUT)
(OUTPUT)
CONDITIONS
C
d
f
pF
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS565F – MARCH 1996 – REVISED JUNE 1998
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
f
max
t
pd
t
en
t
dis
‡
t
sk(o)
†
This information was not available at the time of publication.
‡
Skew between any two outputs of the same package switching in the same direction
FROM
CLK Q † † † † 4.9 1.5 4.5 ns
OE
OE
TO
Q † † † † 5.3 1.5 4.6 ns
Q † † † † 6.1 1.5 5.5 ns
VCC = 1.8 V
± 0.15 V
MIN MAX MIN MAX MIN MAX MIN MAX
† † 150 150 MHz
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
1 ns
operating characteristics, T
PARAMETER
Power dissipation capacitance
p
per flip-flop
†
This information was not available at the time of publication.
= 25°C
A
Outputs enabled
Outputs disabled
TEST
= 10 MHz
VCC = 1.8 V
± 0.15 V
TYP TYP TYP
† † 58
† † 24
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
UNIT
p
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 30 pF
(see Note A)
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCAS565F – MARCH 1996 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
= 1.8 V ± 0.15 V
V
CC
2 × V
Open
GND
CC
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
1k Ω
1k Ω
S1
SN74LVCH16374A
WITH 3-STATE OUTPUTS
Open
2 × V
CC
Open
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN74LVCH16374A
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS565F – MARCH 1996 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
GND
From Output
Under Test
CL = 30 pF
(see Note A)
500 Ω
500 Ω
S1
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH16374A
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS565F – MARCH 1996 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
= 2.7 V AND 3.3 V ± 0.3 V
V
CC
From Output
Under Test
CL = 50 pF
(see Note A)
Timing
Input
Data
Input
Input
t
PLH
Output
500 Ω
500 Ω
LOAD CIRCUIT
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
h
S1
t
PHL
6 V
GND
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
V
V
Open
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
t
w
t
1.5 V
t
1.5 V
Open
6 V
GND
1.5 V1.5 V
PLZ
PHZ
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOL + 0.3 V
VOH – 0.3 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Figure 3. Load Circuit and Voltage Waveforms
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9
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