Datasheet SN74LVCH16373ADGGR, SN74LVCH16373ADGVR, SN74LVCH16373ADL, SN74LVCH16373ADLR Datasheet (Texas Instruments)

SN74LVCH16373A
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS568G – MARCH 1996 – REVISED JUNE 1998
D
D
Widebus EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Typical V
(Output Ground Bounce)
OLP
< 0.8 V at VCC = 3.3 V, TA = 25°C
D
Typical V
(Output VOH Undershoot)
OHV
> 2 V at VCC = 3.3 V, TA = 25°C
D
Power Off Disables Outputs, Permitting Live Insertion
D
Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With
3.3-V VCC)
D
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per JESD 17
D
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
D
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages
description
DGG OR DL PACKAGE
(TOP VIEW)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1OE
1Q1 1Q2
GND
1Q3 1Q4
V
CC
1Q5 1Q6
GND
1Q7 1Q8 2Q1 2Q2
GND
2Q3 2Q4
V
CC
2Q5 2Q6
GND
2Q7 2Q8
2OE
1LE 1D1 1D2 GND 1D3 1D4 V
CC
1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 V
CC
2D5 2D6 GND 2D7 2D8 2LE
This 16-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation. The SN74LVCH16373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. It can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly . The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74LVCH16373A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1998, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1
SN74LVCH16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SCAS568G – MARCH 1996 – REVISED JUNE 1998
OE LE D
L H H H L HL L L LX Q
H X X Z
FUNCTION TABLE
INPUTS
OUTPUT
Q
0
logic symbol
1
1OE
1LE
2OE
2LE
1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8
48 24 25
47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26
1EN C1 2EN C2
3D
4D
2
11 12 13 14 16 17 19 20 22 23
1Q1
3
1Q2
5
1Q3
6
1Q4
8
1Q5
9
1Q6 1Q7 1Q8 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8
1
2
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
1OE
48
1LE
47
1D1
To Seven Other Channels
2
C1 1D
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2
1Q1
2OE
2LE
2D1
24
25
36
C1 1D
To Seven Other Channels
13
2Q1
VCCSuppl
oltage
V
VOOutput voltage
V
IOHHigh-level output current
mA
IOLLow-level output current
mA
SN74LVCH16373A
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS568G – MARCH 1996 – REVISED JUNE 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
–0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
Input voltage range, VI (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 3): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 4)
MIN MAX UNIT
pp
y v
V
V
V
t/v Input transition rise or fall rate 0 10 ns/V T
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 5.5 V
I
p
p
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
Operating 1.65 3.6 Data retention only 1.5 VCC = 1.65 V to 1.95 V 0.65 × V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 2 VCC = 1.65 V to 1.95 V 0.35 × V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 0.8
High or low state 0 V 3 state 0 5.5 VCC = 1.65 V –4 VCC = 2.3 V –8 VCC = 2.7 V –12 VCC = 3 V –24 VCC = 1.65 V 4 VCC = 2.3 V 8 VCC = 2.7 V 12 VCC = 3 V 24
CC
1.7
0.7
CC
V
CC
V
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3
SN74LVCH16373A
V
V
I
mA
1.65 V
2.3 V
()
3 V
I
I
0
3.6 V
A
16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SCAS568G – MARCH 1996 – REVISED JUNE 1998
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS
IOH = –100 µA 1.65 V to 3.6 V VCC–0.2 IOH = –4 mA 1.65 V 1.2
OH
V
OL
I
I
I
I(hold)
I
off
I
OZ
CC
I
CC
C
i
C
All typical values are at VCC = 3.3 V, TA = 25°C.
This information was not available at the time of publication.
§
This is the bus-hold maximum dynamic current required to switch the input from one state to another.
This applies in the disabled state only.
o
IOH = –8 mA 2.3 V 1.7
= –12
OH
IOH = –24 mA 3 V 2.2 IOL = 100 µA 1.65 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.7 IOL = 12 mA 2.7 V 0.4 IOL = 24 mA 3 V 0.55 VI = 0 to 5.5 V 3.6 V ±5 µA VI = 0.58 V VI = 1.07 V VI = 0.7 V VI = 1.7 V VI = 0.8 V VI = 2 V VI = 0 to 3.6 V VI or VO = 5.5 V 0 ±10 µA VO = 0 to 5.5 V 3.6 V ±10 µA VI = VCC or GND
3.6 V ≤ VI 5.5 V One input at VCC – 0.6 V,
Other inputs at VCC or GND VI = VCC or GND 3.3 V 5 pF VO = VCC or GND 3.3 V 6.5 pF
§
=
O
V
CC
2.7 V 2.2 3 V 2.4
3.6 V ±500
2.7 V to 3.6 V 500 µA
MIN TYP†MAX UNIT
V
‡ ‡
45
20 20
µA
µ
–45
75
–75
timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3)
VCC = 1.8 V
± 0.15 V
MIN MAX MIN MAX MIN MAX MIN MAX
t
w
t
su
t
h
This information was not available at the time of publication.
4
Pulse duration, LE high 3.3 3.3 ns Setup time, data before LE 1.7 1.7 ns Hold time, data after LE 1.2 1.2 ns
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
(INPUT)
(OUTPUT)
t
Q
ns
CONDITIONS
C
d
f
pF
SN74LVCH16373A
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS568G – MARCH 1996 – REVISED JUNE 1998
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3)
PARAMETER
pd
t
en
t
dis
This information was not available at the time of publication.
FROM
D
LE OE OE
TO
Q 5.7 1.3 4.7 ns Q 6.3 2.5 5.9 ns
VCC = 1.8 V
± 0.15 V
MIN MAX MIN MAX MIN MAX MIN MAX
4.9 1.6 4.2 † 5.3 2.1 4.6
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
operating characteristics, T
PARAMETER
Power dissipation capacitance
p
per latch
This information was not available at the time of publication.
= 25°C
A
Outputs enabled Outputs disabled
TEST
= 10 MHz
VCC = 1.8 V
± 0.15 V
TYP TYP TYP
39 † 6
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
UNIT
p
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5
SN74LVCH16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SCAS568G – MARCH 1996 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
V
From Output
Under Test
CL = 30 pF
(see Note A)
1k
1k
S1
= 1.8 V ± 0.15 V
CC
2 × V
CC
Open
GND
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
Open
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR10 MHz, ZO = 50 Ω, tr≤2 ns, tf≤2 ns. D. The outputs are measured one at a time with one transition per measurement. E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t are the same as ten. are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
From Output
Under Test
CL = 30 pF
(see Note A)
16-BIT TRANSPARENT D-TYPE LATCH
SCAS568G – MARCH 1996 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
500
500
S1
Open
GND
CC
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
SN74LVCH16373A
WITH 3-STATE OUTPUTS
Open
2 × V
CC
GND
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR10 MHz, ZO = 50 Ω, tr≤2 ns, tf≤2 ns. D. The outputs are measured one at a time with one transition per measurement. E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t are the same as ten. are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
7
SN74LVCH16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SCAS568G – MARCH 1996 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
= 2.7 V AND 3.3 V ± 0.3 V
V
CC
From Output
Under Test
CL = 50 pF
(see Note A)
Timing
Input
Data
Input
Input
t
PLH
Output
500
500
LOAD CIRCUIT
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
h
S1
t
PHL
6 V
GND
Open
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
V
OH
V
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
t
w
t
PLZ
1.5 V
t
PHZ
1.5 V
Open
6 V
GND
1.5 V1.5 V
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOL + 0.3 V
VOH – 0.3 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR10 MHz, ZO = 50 , tr≤2.5 ns, tf≤2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. t
F. t
G. t
PLZ PZL PLH
and t and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
Figure 3. Load Circuit and Voltage Waveforms
8
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.
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