Texas Instruments SN74LVCH162244ADGGR, SN74LVCH162244ADGVR, SN74LVCH162244ADL, SN74LVCH162244ADLR, SN74LVCH162244AGR Datasheet
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SN74LVCH162244A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS545G – OCTOBER 1995 – REVISED JUNE 1999
D
Member of the Texas Instruments
D
Widebus
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Output Ports Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
D
Typical V
(Output Ground Bounce)
OLP
< 0.8 V at VCC = 3.3 V, TA = 25°C
D
Typical V
(Output VOH Undershoot)
OHV
> 2 V at VCC = 3.3 V, TA = 25°C
D
Power Off Disables Outputs, Permitting
Live Insertion
D
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V
D
ESD Protection Exceeds 2000 V Per
CC
)
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR.
DL OR DGG PACKAGE
(TOP VIEW)
1OE
1
48
1Y1
2
47
1Y2
3
46
GND
GND
GND
GND
1Y3
1Y4
V
CC
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
V
CC
4Y1
4Y2
4Y3
4Y4
4OE
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2OE
1A1
1A2
GND
1A3
1A4
V
CC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
V
CC
4A1
4A2
GND
4A3
4A4
3OE
description
This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVCH162244A is designed specifically to improve both the performance and density of 3-state
memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used
as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low
output-enable (OE
The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot
and undershoot.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
) inputs.
Copyright 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN74LVCH162244A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS545G – OCTOBER 1995 – REVISED JUNE 1999
description (continued)
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVCH162244A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OE
L H H
L LL
H X Z
OUTPUT
A
Y
logic symbol
†
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
1
48
25
24
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
EN1
EN2
EN3
EN4
11
12
13
14
16
17
19
20
22
23
2
1Y1
3
1Y2
5
1Y3
6
1Y4
8
2Y1
9
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
1
1
1
2
1
3
1
4
1OE
2OE
3OE
4OE
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
SN74LVCH162244A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS545G – OCTOBER 1995 – REVISED JUNE 1999
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
47
46
44
43
48
41
40
38
37
11
12
25
3OE
2
1Y1
3
1Y2
5
1Y3
6
1Y4
8
2Y1
9
2Y2
2Y3
2Y4
3A1
3A2
3A3
3A4
4OE
4A1
4A2
4A3
4A4
36
35
33
32
24
30
29
27
26
13
14
16
17
19
20
22
23
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, V
(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 3): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
O
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74LVCH162244A
VCCSuppl
oltage
V
VOOutput voltage
V
IOHHigh-level output current
mA
IOLLow-level output current
mA
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS545G – OCTOBER 1995 – REVISED JUNE 1999
recommended operating conditions (see Note 4)
MIN MAX UNIT
pp
y v
V
V
V
∆t/∆v Input transition rise or fall rate 0 10 ns/V
T
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 5.5 V
I
p
p
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
Operating 1.65 3.6
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 0.8
High or low state 0 V
3-state 0 5.5
VCC = 1.65 V –2
VCC = 2.3 V –4
VCC = 2.7 V –8
VCC = 3 V –12
VCC = 1.65 V 2
VCC = 2.3 V 4
VCC = 2.7 V 8
VCC = 3 V 12
CC
1.7
0.7
CC
V
CC
V
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I
mA
I
mA
1.65 V
2.3 V
()
3 V
I
I
0
3.6 V
A
(INPUT)
(OUTPUT)
SN74LVCH162244A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS545G – OCTOBER 1995 – REVISED JUNE 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
IOH = –100 µA 1.65 V to 3.6 V VCC–0.2
IOH = –2 mA 1.65 V 1.2
= –4
V
OH
V
OL
I
I
I
I(hold)
I
off
I
OZ
CC
∆I
CC
C
i
C
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
This information was not available at the time of publication.
§
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
¶
This applies in the disabled state only.
o
OH
IOH = –6 mA 3 V 2.4
IOH = –8 mA 2.7 V 2
IOH = –12 mA 3 V 2
IOL = 100 µA 1.65 V to 3.6 V 0.2
IOL = 2 mA 1.65 V 0.45
= 4
OL
IOL = 6 mA 3 V 0.55
IOL = 8 mA 2.7 V 0.6
IOL = 12 mA 3 V 0.8
VI = 0 to 5.5 V 3.6 V ±5 µA
VI = 0.58 V
VI = 1.07 V
VI = 0.7 V
VI = 1.7 V
VI = 0.8 V
VI = 2 V
VI = 0 to 3.6 V
VI or VO = 5.5 V 0 ±10 µA
VO = 0 to 5.5 V 3.6 V ±10 µA
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V
One input at VCC – 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V 500 µA
VI = VCC or GND 3.3 V 5.5 pF
VO = VCC or GND 3.3 V 6 pF
§
=
¶
O
V
CC
2.3 V 1.7
2.7 V 2.2
2.3 V 0.7
2.7 V 0.4
3.6 V ±500
MIN TYP†MAX UNIT
‡
‡
45
–45
75
–75
20
20
V
V
µA
µ
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
t
pd
t
en
t
dis
‡
This information was not available at the time of publication.
FROM
A Y
OE
OE
TO
Y
Y
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VCC = 1.8 V
± 0.15 V
MIN MAX MIN MAX MIN MAX MIN MAX
‡ ‡ ‡ ‡
‡ ‡ ‡ ‡
‡ ‡ ‡ ‡
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
5.6 1.1 4.4 ns
6.9 1 5.5 ns
6.8 1.8 6.3 ns
UNIT
5
SN74LVCH162244A
CONDITIONS
C
d
f
pF
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS545G – OCTOBER 1995 – REVISED JUNE 1999
operating characteristics, T
PARAMETER
Power dissipation capacitance
p
per buffer/driver
†
This information was not available at the time of publication.
= 25°C
A
Outputs enabled
Outputs disabled
TEST
= 10 MHz
VCC = 1.8 V
± 0.15 V
TYP TYP TYP
VCC = 2.5 V
± 0.2 V
† †
† †
VCC = 3.3 V
± 0.3 V
35
4
UNIT
p
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
(see Note A)
CL = 30 pF
SCAS545G – OCTOBER 1995 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
= 1.8 V ± 0.15 V
V
CC
2 × V
CC
Open
GND
t
1 kΩ
1 kΩ
S1
SN74LVCH162244A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
TEST S1
t
pd
t
PLZ/tPZL
PHZ/tPZH
Open
2 × V
Open
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
h
VCC/2
VCC/2 VCC/2
dis
are the same as tpd.
.
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN74LVCH162244A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS545G – OCTOBER 1995 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 30 pF
(see Note A)
500 Ω
500 Ω
S1
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
GND
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
dis
.
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
(see Note A)
CL = 50 pF
SCAS545G – OCTOBER 1995 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
= 2.7 V AND 3.3 V ± 0.3 V
V
CC
6 V
500 Ω
500 Ω
S1
Open
GND
t
t
SN74LVCH162244A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
TEST S1
t
pd
PLZ/tPZL
PHZ/tPZH
Open
6 V
GND
Timing
Input
Data
Input
Input
Output
LOAD CIRCUIT
t
su
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
t
PLH
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
t
w
2.7 V
2.7 V
0 V
t
h
2.7 V
1.5 V
0 V
2.7 V
0 V
t
PHL
V
OH
V
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 1999, Texas Instruments Incorporated
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