Texas Instruments SN74LVCC4245ADWR, SN74LVCC4245APWLE, SN74LVCC4245APWR, SN74LVCC4245ADBLE, SN74LVCC4245ADBR Datasheet
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OPERATION
SN74LVCC4245A
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS584F – NOVEMBER 1996 – REVISED AUGUST 1998
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
description
This 8-bit (octal) noninverting bus transceiver
uses two separate power-supply rails. The A port,
V
, is dedicated to accept a 5-V supply level,
CCA
and the configurable B port, which is designed to
track V
, accepts voltages from 3 V to 5 V . This
CCB
DB, DW, OR PW PACKAGE
(TOP VIEW)
V
GND
GND
NC – No internal connection
CCA
DIR
A1
A2
A3
A4
A5
A6
A7
A8
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CCB
NC
OE
B1
B2
B3
B4
B5
B6
B7
B8
GND
allows for translation from a 3.3-V to a 5-V
environment and vice versa.
The SN74LVCC4245A is designed for asynchronous communication between data buses. The device
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE
) input can be used to disable the device so the buses are
effectively isolated.
The SN74LVCC4245A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OE DIR
L L B data to A bus
L H A data to B bus
H X Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
1
SN74LVCC4245A
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS584F – NOVEMBER 1996 – REVISED AUGUST 1998
logic diagram (positive logic)
2
DIR
22
OE
3
A1
21
B1
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
IK
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. This value is limited to 6 V maximum.
2. The package thermal impedance is calculated in accordance with JESD 51.
and V
CCA
(see Note 1): I/O ports (A port) –0.5 V to V
I
(see Note 1): (A port) –0.5 V to V
O
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
CCA
JA
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
–0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CCB
I/O ports (B port) –0.5 V to V
Except I/O ports –0.5 V to V
(B port) –0.5 V to V
, V
(see Note 2): DB package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
, or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CCB
DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CCA
CCB
CCA
CCA
CCB
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4.5 V
4.5 V
4.5 V
4.5 V
SN74LVCC4245A
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS584F – NOVEMBER 1996 – REVISED AUGUST 1998
recommended operating conditions (see Note 3)
V
CCA
V
V
V
V
V
V
V
V
V
V
I
OHA
I
OHB
I
OLA
I
OLB
T
NOTE 3: All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI application
Supply voltage 4.5 5 5.5 V
CCA
Supply voltage 2.7 3.3 5.5 V
CCB
High-level input voltage VOB ≤ 0.1 V, VOB ≥ V
IHA
High-level input voltage VOA ≤ 0.1 V, VOA ≥ V
IHB
Low-level input voltage VOB ≤ 0.1 V, VOB ≥ V
ILA
Low-level input voltage VOA ≤ 0.1 V, VOA ≥ V
ILB
Input voltage 0 V
IA
Input voltage 0 V
IB
Output voltage 0 V
OA
Output voltage 0 V
OB
High-level output current 4.5 V 3 V –24 mA
High-level output current 4.5 V 2.7 V to 4.5 V –24 mA
Low-level output current 4.5 V 3 V 24 mA
Low-level output current 4.5 V 2.7 V to 4.5 V 24 mA
Operating free-air temperature –40 85 °C
A
report,
Implications of Slow or Floating CMOS Inputs
– 0.1 V
CCB
5.5 V 5.5 V 2
– 0.1 V
CCA
5.5 V 5.5 V 3.85
– 0.1 V
CCB
5.5 V 5.5 V 0.8
– 0.1 V
CCA
5.5 V 5.5 V 1.65
, literature number SCBA004.
V
CCB
2.7 V 2
3.6 V 2
2.7 V 2
3.6 V 2
2.7 V 0.8
3.6 V 0.8
2.7 V 0.8
3.6 V 0.8
MIN NOM MAX UNIT
CCA
CCB
CCA
CCB
V
V
V
V
V
V
V
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74LVCC4245A
V
V
I
mA
4.5 V
V
V
V
V
IIControl inputs
V
V
GND
5.5 V
A
I
B
V
GND
5.5 V
I
A to B
A
V
GND
I
0
5.5 V
A
‡
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS584F – NOVEMBER 1996 – REVISED AUGUST 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
OHA
OHB
OLA
V
OLB
†
I
OZ
I
CCA
CCB
∆I
CCA
∆I
CCB
C
i
C
io
†
For I/O ports, the parameter IOZ includes the input leakage current.
‡
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or the associated VCC.
A or B ports
B to A
A port
OE
DIR
‡
B port
Control inputs VI = V
A or B ports VO = V
IOH = –100 µA 4.5 V 3 V 4.4 4.49
IOH = –24 mA 4.5 V 3 V 3.76 4.25
IOH = –100 µA 4.5 V 3 V 2.9 2.99
= –12
OH
IOH = –24 mA 4.5 V
IOL = 100 µA 4.5 V 3 V 0.1
IOL = 24 mA 4.5 V 3 V 0.21 0.44
IOL = 100 µA 4.5 V 3 V 0.1
IOL = 12 mA 4.5 V 2.7 V 0.11 0.44
IOL = 24 mA 4.5 V
p
=
I
VO = V
An = VCC or GND 5.5 V Open 8 80
O(A port)
n
VI = V
OE
VI = V
DIR at V
VI = V
OE
VI = V
OE
or
CCA
or GND, VI = VIL or V
CCA/B
= 0,
=
or
CCA
– 2.1 V, Other inputs at V
CCA
at GND and DIR at V
– 2.1 V, Other inputs at V
CCA
CCA
– 2.1 V, Other inputs at V
CCA
at V
CCA
– 0.6 V, Other inputs at V
CCB
at GND and DIR at GND
or GND Open Open 5 pF
CCA
CCA/B
,
or GND
or GND
or GND 5 V 3.3 V 11 pF
=
n
O (B port)
CCA
CCB
or
=
CCA
CCA
CCA
CCB
IH
or GND,
or GND,
or GND,
or GND,
V
CCAVCCB
2.7 V 2.2 2.5
3 V 2.46 2.85
2.7 V 2.1 2.3
3 V 2.25 2.65
4.5 V 3.76 4.25
2.7 V 0.22 0.5
3 V 0.21 0.44
4.5 V 0.18 0.44
3.6 V ±0.1 ±1
5.5 V ±0.1 ±1
5.5 V 3.6 V ±0.5 ±5 µA
3.6 V 8 80
5.5 V 8 80
3.6 V 5 50
5.5 V 8 80
5.5 V 5.5 V 1.35 1.5
5.5 V 5.5 V 1 1.5
5.5 V 3.6 V 1 1.5
5.5 V 3.6 V 0.35 0.5 mA
MIN TYP MAX UNIT
V
µ
µA
µ
mA
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
A
B
ns
B
A
ns
OE
A
ns
OE
B
ns
OE
A
ns
OE
B
ns
CpdPower dissipation capacitance per transceiver
C
pF
SN74LVCC4245A
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS584F – NOVEMBER 1996 – REVISED AUGUST 1998
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figures 1 through 4)
V
PARAMETER
t
PHL
t
PLH
t
PHL
t
PLH
t
PZL
t
PZH
t
PZL
t
PZH
t
PLZ
t
PHZ
t
PLZ
t
PHZ
FROM
(INPUT)
TO
(OUTPUT)
= 5 V
CCA
± 0.5 V,
V
= 5 V
CCB
± 0.5 V
MIN MAX MIN MAX
1 7.1 1 7
1 6 1 7
1 6.8 1 6.2
1 6.1 1 5.3
1 9 1 9
1 8.3 1 8
1 8.2 1 10
1 8.1 1 10.2
1 4.7 1 5.2
1 4.9 1 5.2
1 5.4 1 5.4
1 6.3 1 7.4
V
CCA
± 0.5 V,
V
CCB
TO 3.6 V
= 5 V
= 2.7 V
UNIT
operating characteristics, V
p
p
= 5 V, V
CCA
PARAMETER
p
CCB
= 3.3 V, T
= 25°C
A
Outputs enabled
Outputs disabled
TEST CONDITIONS TYP UNIT
20
= 0,f = 10 MHz
L
6.5
p
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74LVCC4245A
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS584F – NOVEMBER 1996 – REVISED AUGUST 1998
PARAMETER MEASUREMENT INFORMATION FOR A TO B
V
= 4.5 V TO 5.5 V AND V
CCA
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
VOLTAGE WAVEFORMS
PULSE DURATION
Input
t
PLH
Output
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
VOLTAGE WAVEFORMS
NONINVERTING OUTPUTS
500 Ω
500 Ω
t
w
1.5 V1.5 V
1.5 V
1.5 V 1.5 V
t
S1
PHL
3 V
0 V
V
V
OH
OL
6 V
Open
GND
3 V
0 V
Waveform 1
S1 at 6 V
(see Note B)
Waveform 2
S1 at GND
(see Note B)
= 2.7 V TO 3.6 V
CCB
Output
Control
t
PZL
Output
t
Output
PZH
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V
VOLTAGE WAVEFORMS
t
PLZ
1.5 V
t
PHZ
1.5 V
Open
6 V
GND
1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
V
V
[
OL
OH
0 V
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
(see Note A)
Input
Input
Output
CL = 50 pF
t
PROPAGATION DELAY TIMES
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION FOR A TO B
V
= 4.5 V TO 5.5 V AND V
CCA
500 Ω
500 Ω
LOAD CIRCUIT
t
w
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
PLH
1.5 V 1.5 V
VOLTAGE WAVEFORMS
NONINVERTING OUTPUTS
1.5 V
SN74LVCC4245A
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
SCAS584F – NOVEMBER 1996 – REVISED AUGUST 1998
= 3.6 V TO 5.5 V
CCB
7 V
S1
1.5 V1.5 V
t
PHL
3 V
0 V
V
V
GND
3 V
0 V
OH
OL
Open
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
t
PLZ
1.5 V
t
PHZ
1.5 V
Open
7 V
GND
1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3.5 V
V
OL
V
OH
[
0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN74LVCC4245A
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS584F – NOVEMBER 1996 – REVISED AUGUST 1998
PARAMETER MEASUREMENT INFORMATION FOR B TO A
V
= 4.5 V TO 5.5 V AND V
CCA
500 Ω
t
w
500 Ω
1.5 V1.5 V
1.5 V
1.5 V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
VOLTAGE WAVEFORMS
PULSE DURATION
Input
t
PLH
Output
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
1.5 V
VOLTAGE WAVEFORMS
NONINVERTING OUTPUTS
S1
t
PHL
3 V
0 V
V
V
2 × V
GND
3 V
0 V
OH
OL
CCA
Open
Waveform 1
S1 at 2 × V
(see Note B)
Waveform 2
S1 at GND
(see Note B)
= 2.7 V TO 3.6 V
CCB
Output
Control
t
PZL
Output
CCA
t
Output
PZH
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V
1.5 V
VOLTAGE WAVEFORMS
t
PLZ
1.5 V
t
PHZ
Open
2 × V
GND
CCA
1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
V
V
V
[
CCA
OL
OH
0 V
Figure 3. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 50 pF
(see Note A)
Input
Input
Output
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION FOR B TO A
V
= 4.5 V TO 5.5 V AND V
CCA
500 Ω
500 Ω
LOAD CIRCUIT
t
w
/2
CCB
VOLTAGE WAVEFORMS
PULSE DURATION
V
/2
CCB
t
PLH
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
V
1.5 V
CCB
V
/2
S1
CCB
t
PHL
SN74LVCC4245A
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
SCAS584F – NOVEMBER 1996 – REVISED AUGUST 1998
= 3.6 V TO 5.5 V
CCB
2 × V
CCA
Open
GND
V
CCB
/2V
V
0 V
V
V
0 V
CCB
S1 at 2 × V
OH
OL
Output
Control
Output
Waveform 1
CCA
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V
t
PZL
t
PZH
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
t
t
PHZ
PLZ
1.5 V
Open
2 × V
GND
CCA
1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
V
V
V
[
CCA
OL
OH
0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 4. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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