TEXAS INSTRUMENTS SN74LVC86A-EP Technical data

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D OR PW PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7

14
13
12
11
10

9
8

1A
1B
1Y
2A
2B
2Y

GND

V

CC

4B
4A
4Y
3B
3A
3Y

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE

SCAS752B – DECEMBER 2003 – REVISED JULY 2007

FEATURES

• Controlled Baseline • Max tpdof 4.6 ns at 3.3 V
– One Assembly/Test Site, One Fabrication • Typical V

Site at V

CC

• Extended Temperature Performance of –40 ° C • Typical V
to 125 ° C and –55 ° C to 125 ° C V

CC

= 3.3 V, T

• Enhanced Diminishing Manufacturing Sources
(DMS) Support

• Enhanced Product-Change Notification

• Qualification Pedigree

(1)

• Operates From 2 V to 3.6 V

• Inputs Accept Voltages to 5.5 V

(1) Component qualification in accordance with JEDEC and

industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.

(Output Ground Bounce) <0.8 V

OLP

= 3.3 V, T

OHV

= 25 ° C

A

(Output V

= 25 ° C

A

SN74LVC86A-EP

Undershoot) >2 V at

OH

DESCRIPTION/ORDERING INFORMATION

The SN74LVC86A quadruple 2-input exclusive-OR gate is designed for 2.7-V to 3.6-V V
The device performs the Boolean function Y = A ⊕ B or Y = AB + A B in positive logic.
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced

in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the
output.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.

–40 ° C to 125 ° C

–55 ° C to 125 ° C SOIC – D Reel of 2500 SN74LVC86AMDREP LVC86AM

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com .

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

operation.

CC

ORDERING INFORMATION

T

A

SOIC – D Reel of 2500 SN74LVC86AQDREP LVC86AE
TSSOP – PW Reel of 2000 SN74LVC86AQPWREP LVC86AE

PACKAGE

(2)

ORDERABLE PART NUMBER TOP-SIDE MARKING

(1)

FUNCTION TABLE

(EACH GATE)

INPUTS

A B

L L L
L H H
H L H
H H L

OUTPUT

Y

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2003–2007, Texas Instruments Incorporated

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= 1

EXCLUSIVE OR

These five equivalent exclusive-OR symbols are valid for an SN74LVC86A gate in positive logic; negation may be shown at any two ports.

= 2k 2k + 1

LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT ODD-PARITY ELEMENT

The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).

The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.

The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.

SN74LVC86A-EP
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE

SCAS752B – DECEMBER 2003 – REVISED JULY 2007

EXCLUSIVE-OR LOGIC

An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.

Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

V
V
V
I
I
I

θ

T

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of V
(4) The package thermal impedance is calculated in accordance with JESD 51-7.

Supply voltage range –0.5 6.5 V

CC

Input voltage range

I

Output voltage range

O

Input clamp current VI< 0 V –50 mA

IK

Output clamp current VO< 0 V –50 mA

OK

Continuous output current ± 50 mA

O

Continuous current through V

Package thermal impedance

JA

Storage temperature range –65 150 ° C

stg

(2)

(2) (3)

or GND ± 100 mA

CC

(4)

D package 86

–0.5 6.5 V
–0.5 V

PW package 113

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

is provided in the recommended operating conditions table.

CC

+ 0.5 V

CC

° C/W

2

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SN74LVC86A-EP

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE

SCAS752B – DECEMBER 2003 – REVISED JULY 2007

Recommended Operating Conditions

V

V
V
V
V

I

OH

I

OL

Δ t/ Δ v Input transition rise or fall rate 9 ns/V

T

A

(1) All unused inputs of the device must be held at V

Supply voltage V

CC

High-level input voltage V

IH

Low-level input voltage V

IL

Input voltage 0 5.5 V

I

Output voltage 0 V

O

High-level output current mA

Low-level output current mA

Operating free-air temperature ° C

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS V

IOH= –100 μ A 2.7 V to 3.6 V V

V

OH

V

OL

I

I

I

CC

Δ I

CC

C

i

(1) All typical values are at V

IOH= –12 mA V

IOH= –24 mA 3 V 2.2
IOL= 100 μ A 2.7 V to 3.6 V 0.2
IOL= 12 mA 2.7 V 0.4 V
IOL= 24 mA 3 V 0.55
VI= 5.5 V or GND 3.6 V ± 5 μ A
VI= V
One input at V
VI= V

or GND, IO= 0 3.6 V 10 μ A

CC

– 0.6 V, Other inputs at V

CC

or GND 3.3 V 5 pF

CC

= 3.3 V, TA= 25 ° C.

CC

(1)

Operating 2 3.6
Data retention only 1.5

= 2.7 V to 3.6 V 2 V

CC

= 2.7 V to 3.6 V 0.8 V

CC

V

= 2.7 V –12

CC

V

= 3 V –24

CC

V

= 2.7 V 12

CC

V

= 3 V 24

CC

Q suffix –40 125
M suffix –55 125

or GND to ensure proper device operation. See the TI application report,

CC

CC

CC

2.7 V 2.2
3 V 2.4

or GND 2.7 V to 3.6 V 500 μ A

CC

MIN MAX UNIT

MIN TYP

(1)

MAX UNIT

– 0.2

V

CC

Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )

V

= 2.7 V

PARAMETER UNIT

t

pd

FROM TO

(INPUT) (OUTPUT)

A Y 5.6 1 4.6 ns

CC

MIN MAX MIN MAX

Operating Characteristics

TA= 25 ° C

V

= 2.5 V V

PARAMETER UNIT

C

Power dissipation capacitance per gate f = 10 MHz 7.5 8.5 pF

pd

TEST

CONDITIONS

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CC

TYP TYP

V

= 3.3 V

CC

± 0.3 V

= 3.3 V

CC

3

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V

M

t

h

t

su

From Output

Under Test

C

L

(see Note A)

LOAD CIRCUIT

S1

V

LOAD

Open

GND

R

L

R

L

Data Input

Timing Input

V

I

0 V

V

I

0 V

0 V

t

w

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

t

PLH

t

PHL

t

PHL

t

PLH

V

OH

V

OH

V

OL

V

OL

V

I

0 V

Input

Output
Waveform 1
S1 at V

LOAD

(see Note B)

Output
Waveform 2

S1 at GND

(see Note B)

V

OL

V

OH

t

PZL

t

PZH

t

PLZ

t

PHZ

V

LOAD

/2

0 V

VOL + V

∆

VOH - V

∆

≈0 V

V

I

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

V

LOAD

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. t

PLZ

and t

PHZ

are the same as t

dis

.

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

and t

PHL

are the same as tpd.

H. All parameters and waveforms are not applicable to all devices.

Output

Control

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

I

V

M

V

M

2.7 V

3.3 V ± 0.3 V

500 Ω
500 Ω

V

CC

R

L

6 V
6 V

V

LOAD

C

L

50 pF
50 pF

0.3 V

0.3 V

V

∆

2.7 V

2.7 V

V

I

1.5 V

1.5 V

V

M

tr/t

f

≤2.5 ns
≤2.5 ns

INPUTS

SN74LVC86A-EP
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE

SCAS752B – DECEMBER 2003 – REVISED JULY 2007

PARAMETER MEASUREMENT INFORMATION

4

Figure 1. Load Circuit and Voltage Waveforms

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