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D OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
V
CC
4B
4A
4Y
3B
3A
3Y
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
SCAS752B – DECEMBER 2003 – REVISED JULY 2007
FEATURES
• Controlled Baseline • Max tpdof 4.6 ns at 3.3 V
– One Assembly/Test Site, One Fabrication • Typical V
Site at V
CC
• Extended Temperature Performance of –40 ° C • Typical V
to 125 ° C and –55 ° C to 125 ° C V
CC
= 3.3 V, T
• Enhanced Diminishing Manufacturing Sources
(DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree
(1)
• Operates From 2 V to 3.6 V
• Inputs Accept Voltages to 5.5 V
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
(Output Ground Bounce) <0.8 V
OLP
= 3.3 V, T
OHV
= 25 ° C
A
(Output V
= 25 ° C
A
SN74LVC86A-EP
Undershoot) >2 V at
OH
DESCRIPTION/ORDERING INFORMATION
The SN74LVC86A quadruple 2-input exclusive-OR gate is designed for 2.7-V to 3.6-V V
The device performs the Boolean function Y = A ⊕ B or Y = AB + A B in positive logic.
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced
in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the
output.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
–40 ° C to 125 ° C
–55 ° C to 125 ° C SOIC – D Reel of 2500 SN74LVC86AMDREP LVC86AM
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com .
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
operation.
CC
ORDERING INFORMATION
T
A
SOIC – D Reel of 2500 SN74LVC86AQDREP LVC86AE
TSSOP – PW Reel of 2000 SN74LVC86AQPWREP LVC86AE
PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(1)
FUNCTION TABLE
(EACH GATE)
INPUTS
A B
L L L
L H H
H L H
H H L
OUTPUT
Y
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2003–2007, Texas Instruments Incorporated
www.ti.com
= 1
EXCLUSIVE OR
These five equivalent exclusive-OR symbols are valid for an SN74LVC86A gate in positive logic; negation may be shown at any two ports.
= 2k 2k + 1
LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT ODD-PARITY ELEMENT
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
SN74LVC86A-EP
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
SCAS752B – DECEMBER 2003 – REVISED JULY 2007
EXCLUSIVE-OR LOGIC
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
V
V
I
I
I
θ
T
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of V
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Supply voltage range –0.5 6.5 V
CC
Input voltage range
I
Output voltage range
O
Input clamp current VI< 0 V –50 mA
IK
Output clamp current VO< 0 V –50 mA
OK
Continuous output current ± 50 mA
O
Continuous current through V
Package thermal impedance
JA
Storage temperature range –65 150 ° C
stg
(2)
(2) (3)
or GND ± 100 mA
CC
(4)
D package 86
–0.5 6.5 V
–0.5 V
PW package 113
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
is provided in the recommended operating conditions table.
CC
+ 0.5 V
CC
° C/W
2
Submit Documentation Feedback
www.ti.com
SN74LVC86A-EP
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
SCAS752B – DECEMBER 2003 – REVISED JULY 2007
Recommended Operating Conditions
V
V
V
V
V
I
OH
I
OL
Δ t/ Δ v Input transition rise or fall rate 9 ns/V
T
A
(1) All unused inputs of the device must be held at V
Supply voltage V
CC
High-level input voltage V
IH
Low-level input voltage V
IL
Input voltage 0 5.5 V
I
Output voltage 0 V
O
High-level output current mA
Low-level output current mA
Operating free-air temperature ° C
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
IOH= –100 μ A 2.7 V to 3.6 V V
V
OH
V
OL
I
I
I
CC
Δ I
CC
C
i
(1) All typical values are at V
IOH= –12 mA V
IOH= –24 mA 3 V 2.2
IOL= 100 μ A 2.7 V to 3.6 V 0.2
IOL= 12 mA 2.7 V 0.4 V
IOL= 24 mA 3 V 0.55
VI= 5.5 V or GND 3.6 V ± 5 μ A
VI= V
One input at V
VI= V
or GND, IO= 0 3.6 V 10 μ A
CC
– 0.6 V, Other inputs at V
CC
or GND 3.3 V 5 pF
CC
= 3.3 V, TA= 25 ° C.
CC
(1)
Operating 2 3.6
Data retention only 1.5
= 2.7 V to 3.6 V 2 V
CC
= 2.7 V to 3.6 V 0.8 V
CC
V
= 2.7 V –12
CC
V
= 3 V –24
CC
V
= 2.7 V 12
CC
V
= 3 V 24
CC
Q suffix –40 125
M suffix –55 125
or GND to ensure proper device operation. See the TI application report,
CC
CC
CC
2.7 V 2.2
3 V 2.4
or GND 2.7 V to 3.6 V 500 μ A
CC
MIN MAX UNIT
MIN TYP
(1)
MAX UNIT
– 0.2
V
CC
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )
V
= 2.7 V
PARAMETER UNIT
t
pd
FROM TO
(INPUT) (OUTPUT)
A Y 5.6 1 4.6 ns
CC
MIN MAX MIN MAX
Operating Characteristics
TA= 25 ° C
V
= 2.5 V V
PARAMETER UNIT
C
Power dissipation capacitance per gate f = 10 MHz 7.5 8.5 pF
pd
TEST
CONDITIONS
Submit Documentation Feedback
CC
TYP TYP
V
= 3.3 V
CC
± 0.3 V
= 3.3 V
CC
3
www.ti.com
V
M
t
h
t
su
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
S1
V
LOAD
Open
GND
R
L
R
L
Data Input
Timing Input
V
I
0 V
V
I
0 V
0 V
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
V
I
0 V
Input
Output
Waveform 1
S1 at V
LOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
V
LOAD
/2
0 V
VOL + V
∆
VOH - V
∆
≈0 V
V
I
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
V
LOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
I
V
M
V
M
2.7 V
3.3 V ± 0.3 V
500 Ω
500 Ω
V
CC
R
L
6 V
6 V
V
LOAD
C
L
50 pF
50 pF
0.3 V
0.3 V
V
∆
2.7 V
2.7 V
V
I
1.5 V
1.5 V
V
M
tr/t
f
≤2.5 ns
≤2.5 ns
INPUTS
SN74LVC86A-EP
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
SCAS752B – DECEMBER 2003 – REVISED JULY 2007
PARAMETER MEASUREMENT INFORMATION
4
Figure 1. Load Circuit and Voltage Waveforms
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device Status
SN74LVC86AMDREP ACTIVE SOIC D 14 2500 Green (RoHS &
SN74LVC86AQDREP ACTIVE SOIC D 14 2500 Green (RoHS &
SN74LVC86AQPWREP ACTIVE TSSOP PW 14 2000 Green (RoHS &
V62/04670-01XE ACTIVE SOIC D 14 2500 Green (RoHS &
V62/04670-01YE ACTIVE TSSOP PW 14 2000 Green (RoHS &
V62/04670-02XE ACTIVE SOIC D 14 2500 Green (RoHS &
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC86A-EP :
Catalog: SN74LVC86A
•
Automotive: SN74LVC86A-Q1
•
Military: SN54LVC86A
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
SN74LVC86AMDREP SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC86AQDREP SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC86AQPWREP TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)B0(mm)K0(mm)P1(mm)W(mm)
Quadrant
Pin1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Jul-2010
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC86AMDREP SOIC D 14 2500 333.2 345.9 28.6
SN74LVC86AQDREP SOIC D 14 2500 333.2 345.9 28.6
SN74LVC86AQPWREP TSSOP PW 14 2000 346.0 346.0 29.0
Pack Materials-Page 2
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