Texas Instruments SN74LVC828APWR, SN74LVC828ADBLE, SN74LVC828ADBR, SN74LVC828ADGVR, SN74LVC828ADW Datasheet
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SN74LVC828A
10-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS347E – MARCH 1994 – REVISED JUNE 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
T ypical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, TA = 25°C
D
T ypical V
OHV
(Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
D
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V VCC)
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
description
This 10-bit buffer/bus driver is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC828A provides a high-performance bus interface for wide data paths or buses carrying parity.
The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1
or OE2)
input is high, all ten outputs are in the high-impedance state. The SN74LVC828A provides inverting data at
its outputs.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVC828A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUT
OE1 OE2 A
Y
L L L H
L LH L
H XX Z
X H X Z
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
DB, DW, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
GND
V
CC
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
OE2
SN74LVC828A
10-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS347E – MARCH 1994 – REVISED JUNE 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
2
A1
3
A2
4
A3
5
A4
6
A5
Y1
23
Y2
22
Y3
21
Y4
20
Y5
19
Y6
18
Y7
17
Y8
16
7
A6
8
A7
9
A8
13
1
OE1
OE2
EN
&
Y9
15
Y10
14
10
A9
11
A10
1
logic diagram (positive logic)
Y1
To Nine Other Channels
OE1
OE2
A1
1
13
223
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage range, VCC –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 ) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 3): DB package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
SN74LVC828A
10-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS347E – MARCH 1994 – REVISED JUNE 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN MAX UNIT
pp
Operating 1.65 3.6
VCCSuppl
y v
oltage
Data retention only 1.5
V
VCC = 1.65 V to 1.95 V 0.65 × V
CC
V
IH
High-level input voltage
VCC = 2.3 V to 2.7 V
1.7
V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V
CC
V
IL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
V
VCC = 2.7 V to 3.6 V 0.8
V
I
Input voltage 0 5.5 V
p
High or low state 0 V
CC
VOOutput voltage
3 state 0 5.5
V
VCC = 1.65 V –4
p
VCC = 2.3 V –8
IOHHigh-level output current
VCC = 2.7 V –12
mA
VCC = 3 V –24
VCC = 1.65 V 4
p
VCC = 2.3 V 8
IOLLow-level output current
VCC = 2.7 V 12
mA
VCC = 3 V 24
∆t/∆v Input transition rise or fall rate 0 10 ns/V
T
A
Operating free-air temperature –40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
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