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SN74LVC827
10-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS306B – MARCH 1993 – REVISED JUL Y 1995
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Typical V
< 0.8 V at V
D
Typical V
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
(Output VOH Undershoot)
OHV
> 2 V at VCC = 3.3 V, TA = 25°C
D
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
description
DB, DW, OR PW PACKAGE
(TOP VIEW)
OE1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
OE2
This 10-bit buffer/bus driver is designed for 2.7-V
to 3.6-V VCC operation.
The SN74LVC827 provides a high-performance bus interface for wide data paths or buses carrying parity.
The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1
input is high, all ten outputs are in the high-impedance state. The SN74L VC827 provides true data at its outputs.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
or OE2)
The SN74LVC827 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OE1 OE2 A
L L L L
L LH H
H XX Z
X H X Z
OUTPUT
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1995, Texas Instruments Incorporated
1
SN74LVC827
10-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS306B – MARCH 1993 – REVISED JUL Y 1995
1
13
2
3
4
5
6
7
8
9
10
11
†
&
EN
1
23
22
21
20
19
18
17
16
15
14
logic diagram (positive logic)
1
OE1
13
OE2
2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
A1 Y1
23
To Nine Other Channels
logic symbol
OE1
OE2
A1
A2
A3
A4
A5
A6
A7
A8
A9 Y9
A10 Y10
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage range, V
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
Input voltage range, VI (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 ) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 3):DB package 0.65 W. . . . . . . . . . . . . . . . .
DW package 1.7 W. . . . . . . . . . . . . . . . .
PW package 0.7 W. . . . . . . . . . . . . . . . . .
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Data Book
, literature number SCBD002B.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Package Thermal Considerations
application note in the 1994
ABT Advanced BiCMOS T echnology
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IOHHigh-level output current
mA
IOLLow-level output current
mA
V
I
mA
V
(INPUT)
(OUTPUT)
SN74LVC827
10-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS306B – MARCH 1993 – REVISED JUL Y 1995
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
CC
V
IH
V
IL
V
I
V
O
∆t/∆v Input transition rise or fall rate 0 10 ns/V
T
A
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
‡
All typical values are at VCC = 3.3 V, TA = 25°C.
Supply voltage 2.7 3.6 V
High-level input voltage VCC = 2.7 V to 3.6 V 2 V
Low-level input voltage VCC = 2.7 V to 3.6 V 0.8 V
Input voltage 0 5.5 V
Output voltage 0 V
p
p
Operating free-air temperature –40 85 °C
PARAMETER TEST CONDITIONS
IOH = –100 µA MIN to MAX VCC–0.2
= –12
OH
IOH = – 24 mA 3 V 2
IOL = 100 µA MIN to MAX 0.2
IOL = 12 mA 2.7 V 0.4
IOL = 24 mA 3 V 0.55
VI = 5.5 V or GND 3.6 V ±5 µA
VO = VCC or GND 3.6 V ±10 µA
VI = VCC or GND, IO = 0 3.6 V 20 µA
One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 500 µA
VI = VCC or GND 3.3 V 9 pF
VO = VCC or GND 3.3 V 10 pF
V
I
I
I
n
C
C
OH
OL
I
OZ
CC
i
o
I
CC
VCC = 2.7 V –12
VCC = 3 V –24
VCC = 2.7 V 12
VCC = 3 V 24
†
V
CC
2.7 V 2.2
3 V 2.4
MIN TYP‡MAX UNIT
CC
V
V
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
t
pd
t
en
t
dis
FROM
A Y 1.5 7 8 ns
OE Y 1.5 9 11 ns
OE Y 1.5 8 9 ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TO
VCC = 3.3 V
± 0.3 V
MIN MAX MIN MAX
VCC = 2.7 V
UNIT
3
SN74LVC827
CpdPower dissipation capacitance per buffer/driver
C
pF
10-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS306B – MARCH 1993 – REVISED JUL Y 1995
operating characteristics, VCC = 3.3 V, TA = 25°C
PARAMETER
p
p
p
PARAMETER MEASUREMENT INFORMATION
Outputs enabled
Outputs disabled
TEST CONDITIONS TYP UNIT
p
= 50 pF, f = 10 MHz
L
25
2.5
p
500 Ω
t
w
1.5 V
500 Ω
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR OUTPUTS
Input
Output
Output
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
Input
t
PLH
t
PHL
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V 1.5 V
VOLTAGE WAVEFORMS
S1
t
PHL
1.5 V
t
PLH
1.5 V1.5 V
6 V
2.7 V
0 V
V
OH
V
OL
V
OH
V
OL
Open
GND
2.7 V
0 V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
t
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
su
t
1.5 V
t
PHZ
1.5 V
PLZ
Open
6 V
GND
1.5 V
t
h
1.5 V
VOL + 0.3 V
VOH – 0.3 V
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
[
0 V
NOTES: A. CL includes probe and jig capacitance.
4
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
.
dis
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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