Texas Instruments SN74LVC74AD, SN74LVC74ADBLE, SN74LVC74ADBR, SN74LVC74ADR, SN74LVC74APWLE Datasheet

SN54LVC74A, SN74LVC74A

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLEAR AND PRESET

SCAS287H – JANUARY 1993 – REVISED JUNE 1998

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

Typical V
< 0.8 V at V

D

Typical V
> 2 V at V

D

Inputs Accept Voltages to 5.5 V

D

Package Options Include Plastic

(Output Ground Bounce)

OLP

= 3.3 V, TA = 25°C

CC

(Output VOH Undershoot)

OHV

= 3.3 V, TA = 25°C

CC

SN54LVC74A...J OR W PACKAGE

SN74LVC74A. . . D, DB, OR PW PACKAGE

SN54LVC74A. . . FK PACKAGE

1CLR

1D
1CLK
1PRE

1Q

1Q

GND

(TOP VIEW)

1

14

2

13

3

12

4

11

5

10
6
7

(TOP VIEW)

9
8

V

CC

2CLR
2D
2CLK
2PRE
2Q
2Q

Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, and Ceramic Flat (W) Packages,
Ceramic Chip Carriers (FK), and DIPs (J)

description

The SN54LVC74A dual positive-edge-triggered
D-type flip-flop is designed for 2.7-V to 3.6-V V
operation and the SN74LVC74A dual positive­edge-triggered D-type flip-flop is designed for

1.65-V to 3.6-V V
A low level at the preset (PRE

operation.

CC

) or clear (CLR)

CC

1D

1CLK

NC

1PRE

NC

1Q

NC – No internal connection

3212019

4
5
6
7
8

910111213

1Q

1CLR

NC

NC

GND

V

CC

2Q

2CLR

18
17
16
15
14

2Q

2D
NC
2CLK
NC
2PRE

inputs sets or resets the outputs, regardless of the
levels of the other inputs. When PRE

and CLR are
inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on
the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related
to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without
affecting the levels at the outputs.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.

The SN54L VC74A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LVC74A is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1998, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

1

SN54LVC74A, SN74LVC74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET

SCAS287H – JANUARY 1993 – REVISED JUNE 1998

FUNCTION TABLE

INPUTS

PRE CLR CLK D Q Q

L H X X H L
H LXXLH
LLXXH
HH↑HHL
HH↑LLH
HHLXQ

†

This configuration is unstable; that is, it does not
persist when PRE
(high) level.

or CLR returns to its inactive

OUTPUTS

†

0

†

H

Q

0

logic symbol

‡

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, J, PW, and W packages.

‡

1PRE

1CLK

1D

1CLR

2PRE

2CLK

2D

2CLR

4
3
2
1

10
11
12
13

S

C1
1D
R

logic diagram, each flip-flop (positive logic)

PRE

CLK

C

C

C

TG

5

1Q

6

1Q

9

2Q

8

2Q

Q

2

CLR

C

D

TG

C

C

C

TG

C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

C

TG

Q

C

UNIT

VCCSuppl

oltage

V

IOHHigh-level output current

mA

IOLLow-level output current

mA

SN54LVC74A, SN74LVC74A

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLEAR AND PRESET

SCAS287H – JANUARY 1993 – REVISED JUNE 1998

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply-voltage range, V
Input-voltage range, V
Output-voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ

–0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 3): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

†

DB package 158°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The value of VCC is provided in the recommended operating conditions table.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 4)

SN54LVC74A SN74LVC74A

MIN MAX MIN MAX

pp

y v

V

V

V
V

∆t/∆v Input transition rise or fall rate 0 10 0 10 ns/V
T

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

High-level input voltage

IH

Low-level input voltage

IL

Input voltage 0 5.5 0 5.5 V

I

Output voltage 0 V

O

p

p

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

Operating 2 3.6 1.65 3.6
Data retention only 1.5 1.5
VCC = 1.65 V to 1.95 V 0.65×V
VCC = 2.3 V to 2.7 V 1.7
VCC = 2.7 V to 3.6 V 2 2
VCC = 1.65 V to 1.95 V 0.35×V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 0.8 0.8

CC

VCC = 1.65 V –4
VCC = 2.3 V –8
VCC = 2.7 V –12 –12
VCC = 3 V –24 –24
VCC = 1.65 V 4
VCC = 2.3 V 8
VCC = 2.7 V 12 12
VCC = 3 V 24 24

, literature number SCBA004.

CC

0 V

0.7

CC

V

CC

V

V

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