Texas Instruments SN74LVC652ADBLE, SN74LVC652ADBR, SN74LVC652ADGVR, SN74LVC652ADW, SN74LVC652ADWR Datasheet
...
SN54LVC652A, SN74LVC652A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS303H – JANUARY 1993 – REVISED AUGUST 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
T ypical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, TA = 25°C
D
T ypical V
OHV
(Output VOH Undershoot)
> 2 V at V
CC
= 3.3 V, TA = 25°C
D
Support Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V
CC
)
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW)
Packages, and Ceramic Chip Carriers (FK)
description
The SN54LVC652A octal bus transceiver and
register is designed for 2.7-V to 3.6-V V
CC
operation, and the SN74LVC652A octal bus
transceiver and register is designed for 1.65-V to
3.6-V V
CC
operation.
These devices consist of bus transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Output-enable (OEAB and OEBA
) inputs are
provided to control the transceiver functions.
Select-control (SAB and SBA) inputs are provided
to select whether real-time or stored data is
transferred. The circuitry used for select control
eliminates the typical decoding glitch that occurs
in a multiplexer during the transition between stored and real-time data. A low input selects real-time data, and
a high input selects stored data. Figure 1 illustrates the four fundamental bus-management functions that are
performed with the ’LVC652A.
Data on the A or B data bus, or both, is stored in the internal D-type flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by
simultaneously enabling OEAB and OEBA
. In this configuration, each output reinforces its input. When all other
data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
SN74LVC652A. . . DB, DW, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLKAB
SAB
OEAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
CLKBA
SBA
OEBA
B1
B2
B3
B4
B5
B6
B7
B8
SN54LVC652A. . . FK PACKAGE
(TOP VIEW)
3212827
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
OEBA
B1
B2
NC
B3
B4
B5
A1
A2
A2
NC
A4
A5
A6
426
14 15 16 17 18
A7
A8
GND
NC
B8B7B6
OEAB
SAB
CLKABNCCLKBA
SBA
V
CC
NC – No internal connection
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54LVC652A, SN74LVC652A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS303H – JANUARY 1993 – REVISED AUGUST 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor
is determined by the current-sinking/current-sourcing capability of the driver.
The SN54L VC652A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVC652A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
DATA I/O
†
OEAB OEBA CLKAB CLKBA SAB SBA A1–A8 B1–B8
OPERATION OR FUNCTION
L H H or L H or L X X Input Input Isolation
L H ↑↑X X Input Input Store A and B data
X H ↑ H or L X X Input Unspecified
‡
Store A, hold B
H H ↑↑X
‡
X Input Output Store A in both registers
L X H or L ↑ X X Unspecified
‡
Input Hold A, store B
L L ↑↑XX
‡
Output Input Store B in both registers
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
H H X X L X Input Output Real-time A data to B bus
H H H or L X H X Input Output Stored A data to B bus
H L H or L H or L H H Output Output
Stored A data to B bus and
stored B data to A bus
†
The data-output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always are
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
‡
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
SN54LVC652A, SN74LVC652A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS303H – JANUARY 1993 – REVISED AUGUST 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OEAB
X
L
L
OEAB
LL
CLKABXCLKBAXSABXSBA
L
CLKABXCLKBAXSABLSBA
X
H
CLKAB CLKBAXSABXSBA
X
CLKAB CLKBA SAB SBA
X
H
XX
X
X
X
H L H or L H H
↑
↑
↑↑
OEBA
OEBA
HH
OEAB OEBA
OEAB OEBA
H or L
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
3 21 1 23 2 22 1 23 2 22321
3 21 23 2 22 3 21 1 2 22
1
23
Figure 1. Bus-Management Functions
SN54LVC652A, SN74LVC652A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS303H – JANUARY 1993 – REVISED AUGUST 1998
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, and PW packages.
OEBA
EN1 [BA]
21
G5
22
SBA
A1
4
B1
20
4D
EN2 [AB]
3
OEAB
23
CLKBA
1
CLKAB
G7
2
SAB
5
7
7
5
1
1
6D ≥1
≥1
1
2
C6
C4
A2
5
B2
19
A3
6
B3
18
A4
7
B4
17
A5
8
B5
16
A6
9
B6
15
A7
10
B7
14
A8
11
B8
13
SN54LVC652A, SN74LVC652A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS303H – JANUARY 1993 – REVISED AUGUST 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
OEBA
A1
B1
1D
C1
1D
C1
One of Eight Channels
SAB
CLKAB
SBA
CLKBA
OEAB
To Seven Other Channels
21
3
23
22
1
2
4
20
Pin numbers shown are for the DB, DW, and PW packages.
SN54LVC652A, SN74LVC652A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS303H – JANUARY 1993 – REVISED AUGUST 1998
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 3): DB package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVC652A SN74LVC652A
MIN MAX MIN MAX
UNIT
pp
Operating 2 3.6 1.65 3.6
VCCSuppl
y v
oltage
Data retention only 1.5 1.5
V
VCC = 1.65 V to 1.95 V 0.65 × V
CC
V
IH
High-level input voltage
VCC = 2.3 V to 2.7 V
1.7
V
VCC = 2.7 V to 3.6 V 2 2
VCC = 1.65 V to 1.95 V 0.35 × V
CC
V
IL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
V
VCC = 2.7 V to 3.6 V 0.8 0.8
V
I
Input voltage 0 5.5 0 5.5 V
p
High or low state 0 V
CC
0 V
CC
VOOutput voltage
3 state 0 5.5 0 5.5
V
VCC = 1.65 V –4
p
VCC = 2.3 V –8
IOHHigh-level output current
VCC = 2.7 V –12 –12
mA
VCC = 3 V –24 –24
VCC = 1.65 V 4
p
VCC = 2.3 V 8
IOLLow-level output current
VCC = 2.7 V 12 12
mA
VCC = 3 V 24 24
∆t/∆v Input transition rise or fall rate 0 5 0 5 ns/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
SN54LVC652A, SN74LVC652A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS303H – JANUARY 1993 – REVISED AUGUST 1998
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVC652A SN74LVC652A
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP†MAX MIN TYP†MAX
UNIT
1.65 V to 3.6 V VCC–0.2
I
OH
= –
100 µA
2.7 V to 3.6 V VCC–0.2
IOH = –4 mA 1.65 V 1.2
V
OH
IOH = –8 mA 2.3 V 1.7
V
2.7 V 2.2 2.2
I
OH
= –12
mA
3 V 2.4 2.4
IOH = –24 mA 3 V 2.2 2.2
1.65 V to 3.6 V 0.2
I
OL
=
100 µA
2.7 V to 3.6 V 0.2
IOL = 4 mA 1.65 V 0.45
V
OL
IOL = 8 mA 2.3 V 0.7
V
IOL = 12 mA 2.7 V 0.4 0.4
IOL = 24 mA 3 V 0.55 0.55
I
I
Control inputs VI = 0 to 5.5 V 3.6 V ±5 ±5 µA
I
off
VI or VO = 5.5 V 0 ±10 µA
I
OZ
‡
VO = 0 to 5.5 V 3.6 V ±15 ±10 µA
VI = VCC or GND
10 10
I
CC
3.6 V ≤ VI ≤ 5.5 V
§
I
O
=
0
3.6 V
10 10
µ
A
∆I
CC
One input at VCC – 0.6 V,
Other inputs at
VCC or GND
2.7 V to 3.6 V 500 500 µA
C
i
Control inputs VI = VCC or GND 3.3 V 4.5 4.5 pF
C
io
A or B ports VO = VCC or GND 3.3 V 7.5 7.5 pF
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
For I/O ports, the parameter IOZ includes the input leakage current.
§
This applies in the disabled state only.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 4)
SN54LVC652A
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
MIN MAX MIN MAX
f
clock
Clock frequency 80 100 MHz
t
w
Pulse duration 3.3 3.3 ns
t
su
Setup time, data before CLK↑
1.6 1.5 ns
t
h
Hold time, data after CLK↑
0.5 1.5 ns
SN54LVC652A, SN74LVC652A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS303H – JANUARY 1993 – REVISED AUGUST 1998
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 4)
SN74LVC652A
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
f
clock
Clock frequency † † 80 100 MHz
t
w
Pulse duration † † 3.3 3.3 ns
t
su
Setup time, data before CLK↑
† † 1.9 1.9 ns
t
h
Hold time, data after CLK↑
† † 1.5 1.7 ns
†
This information was not available at the time of publication.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 4)
SN54LVC652A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
MIN MAX MIN MAX
f
max
80 100 MHz
A or B B or A 7.8 1 7.4
t
pd
CLK A or B 8.4 1 8
ns
SAB or SBA B or A 9.6 1 8.7
t
en
OEBA
A 8.9 1 7.4 ns
t
dis
OEBA
A 8.1 1 7.5 ns
t
en
OEAB
B 8.6 1 7.1 ns
t
dis
OEAB
B 7.7 1 7.4 ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 4)
SN74LVC652A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
f
max
† † 80 100 MHz
A or B B or A † † † † 7.8 1.5 7.4
t
pd
CLK A or B † † † † 8.4 1.5 8
ns
SAB or SBA B or A † † † † 9.6 1.5 8.7
t
en
OEBA
A † † † † 8.9 1.5 7.4 ns
t
dis
OEBA
A † † † † 8.1 1.5 7.5 ns
t
en
OEAB
B † † † † 8.6 1.5 7.1 ns
t
dis
OEAB
B † † † † 7.7 1.5 7.4 ns
†
This information was not available at the time of publication.
SN54LVC652A, SN74LVC652A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS303H – JANUARY 1993 – REVISED AUGUST 1998
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics, T
A
= 25°C
PARAMETER
TEST
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
UNIT
CONDITIONS
TYP TYP TYP
Power dissipation capacitance
Outputs enabled
† † 84
p
C
p
d
per transceiver
Outputs disabled
f
= 10 MHz
† † 9.5
pF
†
This information was not available at the time of publication.
SN54LVC652A, SN74LVC652A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS303H – JANUARY 1993 – REVISED AUGUST 1998
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 1.8 V ± 0.15 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
1 kΩ
1 kΩ
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
V
CC
0 V
0 V
t
w
V
CC
V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO = 50 Ω, tr≤2 ns, tf≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
0 V
V
CC
VCC/2
t
PHL
VCC/2 VCC/2
V
CC
0 V
V
OH
V
OL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
t
PLH
2 × V
CC
V
CC
Figure 2. Load Circuit and Voltage Waveforms
SN54LVC652A, SN74LVC652A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS303H – JANUARY 1993 – REVISED AUGUST 1998
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.5 V ± 0.2 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
V
CC
0 V
0 V
t
w
V
CC
V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO = 50 Ω, tr≤2 ns, tf≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
0 V
V
CC
VCC/2
t
PHL
VCC/2 VCC/2
V
CC
0 V
V
OH
V
OL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
t
PLH
2 × V
CC
V
CC
Figure 3. Load Circuit and Voltage Waveforms
SN54LVC652A, SN74LVC652A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS303H – JANUARY 1993 – REVISED AUGUST 1998
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.7 V AND 3.3 V ± 0.3 V
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
6 V
Open
GND
500 Ω
500 Ω
t
PLH
t
PHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V1.5 V
1.5 V 1.5 V
2.7 V
0 V
1.5 V 1.5 V
V
OH
V
OL
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
0 V
1.5 V
2.7 V
0 V
1.5 V 1.5 V
0 V
2.7 V
0 V
1.5 V 1.5 V
t
w
Input
2.7 V
2.7 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO = 50 Ω, tr≤2.5 ns, tf≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
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Copyright 1998, Texas Instruments Incorporated
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