DB, DW, OR PW PACKAGE
(TOP VIEW)
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SN74LVC646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS302A – JANUARY 1993 – REVISED JUL Y 1995
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
T ypical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, TA = 25°C
D
T ypical V
OHV
(Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
D
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
description
This octal bus transceiver and register is designed for 2.7-V to 3.6-V VCC operation.
The SN74LVC646 consists of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus
is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input.
Figure 1 illustrates the four fundamental bus-management functions that can be performed with the
SN74LVC646.
Output-enable (OE
) and direction-control (DIR) inputs control the transceiver functions. In the transceiver
mode, data present at the high-impedance port can be stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR
determines which bus receives data when OE
is low. In the isolation mode (OE high), A data can be stored in
one register and B data can be stored in the other register.
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVC646 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
DATA I/Os
OE DIR CLKAB CLKBA SAB SBA A1 – A8 B1 – B8
OPERATION OR FUNCTION
X X ↑ X X X Input Unspecified
†
Store A, B unspecified
†
X XX ↑ X X Unspecified
†
Input Store B, A unspecified
†
H X ↑ ↑ X X Input Input Store A and B data
H X H or L H or L X X Input disabled Input disabled Isolation, hold storage
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
L H X X L X Input Output Real-time A data to B bus
L H H or L X H X Input Output Stored A data to B bus
†
The data output functions may be enabled or disabled by various signals at the OE
and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins is stored on every low-to-high transition of the clock inputs.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74LVC646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS302A – JANUARY 1993 – REVISED JUL Y 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
L
3
DIR
L
1
CLKAB
X
23
CLKBA
X
2
SAB
X
22
SBA
L
REAL-TIME TRANSFER
BUS B TO BUS A
21
L
3
DIR
H
1
CLKAB
X
23
CLKBA
X
2
SAB
L
22
SBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
21
X
3
DIR
X
1
CLKAB23CLKBA
X
2
SAB
X
22
SBA
X
STORAGE FROM
A, B, OR A AND B
21
L
3
DIR
L
1
CLKAB
X
23
CLKBA
H or L
2
SAB
X
22
SBA
H
TRANSFER STORED DATA
TO A AND/OR B
X
H
X
X
XX
X
X
X
L H H or L X H X
↑
↑
↑↑
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OE
OE
OEOE
Figure 1. Bus-Management Functions
SN74LVC646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS302A – JANUARY 1993 – REVISED JUL Y 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
OE
G3
21
3 EN2 [AB]
G5
22
SBA
A2
5
A3
6
A4
7
A5
8
A6
9
A7
10
A8
11
A1
4
B1
20
4D
B2
19
B3
18
B4
17
B5
16
B6
15
B7
14
B8
13
3 EN1 [BA]
3
DIR
23
CLKBA
1
CLKAB
G7
2
SAB
5
7
7
5
1
1
6D ≥1
≥1
1
2
C6
C4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN74LVC646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS302A – JANUARY 1993 – REVISED JUL Y 1995
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
A1
B1
1D
C1
1D
C1
One of Eight
Channels
20
4
2
1
22
23
21
3
SAB
CLKAB
SBA
CLKBA
DIR
OE
To Seven Other Channels
SN74LVC646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS302A – JANUARY 1993 – REVISED JUL Y 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI: Except I/O ports (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O ports (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 3):DB package 0.65 W. . . . . . . . . . . . . . . . .
DW package 1.7 W. . . . . . . . . . . . . . . . .
PW package 0.7 W. . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Package Thermal Considerations
application note in the 1994
ABT Advanced BiCMOS T echnology
Data Book
, literature number SCBD002B.
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
CC
Supply voltage 2.7 3.6 V
V
IH
High-level input voltage VCC = 2.7 V to 3.6 V 2 V
V
IL
Low-level input voltage VCC = 2.7 V to 3.6 V 0.8 V
p
Control inputs 0 5.5
VIInput voltage
Data inputs 0 V
CC
V
V
O
Output voltage 0 V
CC
V
p
VCC = 2.7 V –12
IOHHigh-level output current
VCC = 3 V –24
mA
p
VCC = 2.7 V 12
IOLLow-level output current
VCC = 3 V 24
mA
∆t/∆v Input transition rise or fall rate 0 10 ns/V
T
A
Operating free-air temperature –40 85 °C
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
SN74LVC646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS302A – JANUARY 1993 – REVISED JUL Y 1995
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
V
CC
†
MIN TYP‡MAX UNIT
IOH = –100 µA MIN to MAX VCC–0.2
2.7 V 2.2
VOHI
OH
= –12
mA
3 V 2.4
V
IOH = – 24 mA 3 V 2
IOL = 100 µA MIN to MAX 0.2
V
OL
IOL = 12 mA 2.7 V 0.4
V
IOL = 24 mA 3 V 0.55
I
I
VI = 5.5 V or GND 3.6 V ±5 µA
I
OZ
§
VO = VCC or GND 3.6 V ±10 µA
I
CC
VI = VCC or GND, IO = 0 3.6 V 20 µA
n
I
CC
One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 500 µA
C
i
Control
inputs
VI = VCC or GND 3.3 V 4.6 pF
C
io
A or B
ports
VO = VCC or GND 3.3 V 7.2 pF
†
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
‡
All typical values are measured at VCC = 3.3 V, TA = 25°C.
§
For I/O ports, the parameter IOZ includes the input leakage current.
timing characteristics over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 2)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN MAX MIN MAX
t
w
Pulse duration 5 5 ns
t
su
Setup time, data before CLK↑ 5 5 ns
t
h
Hold time, data after CLK↑ 1 1 ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 2)
PARAMETER
FROM
TO
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
(INPUT)
(OUTPUT)
MIN MAX MIN MAX
f
max
100 80 MHz
A or B B or A 1.5 8 9.2
t
pd
CLK A or B 1.5 9 11
ns
SBA or SAB A or B 1.5 9 11
t
en
OE A or B 1.5 8.5 9.5 ns
t
dis
OE A or B 1.5 8.5 9.5 ns
t
en
DIR A or B 1.5 9 10 ns
t
dis
DIR A or B 1.5 9 10 ns
SN74LVC646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS302A – JANUARY 1993 – REVISED JUL Y 1995
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics, V
CC
= 3.3 V, TA = 25°C
PARAMETER
TEST CONDITIONS TYP UNIT
p
p
p
Outputs enabled
p
38
p
CpdPower dissipation capacitance per transceiver
Outputs disabled
C
L
= 50 pF, f = 10 MHz
4.2
pF
PARAMETER MEASUREMENT INFORMATION
1.5 V
t
h
t
su
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR OUTPUTS
S1
6 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input
1.5 V
2.7 V
0 V
1.5 V
1.5 V
2.7 V
0 V
2.7 V
0 V
1.5 V
1.5 V
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
1.5 V 1.5 V
2.7 V
0 V
1.5 V
1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V
1.5 V
3 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
[
0 V
2.7 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
SN74LVC646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS302A – JANUARY 1993 – REVISED JUL Y 1995
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1999, Texas Instruments Incorporated
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