Texas Instruments SN74LVC646ADBLE, SN74LVC646ADBR, SN74LVC646ADW, SN74LVC646ADWR, SN74LVC646APWLE Datasheet
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SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS302G – JANUARY 1993 – REVISED JUNE1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
T ypical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, TA = 25°C
D
T ypical V
OHV
(Output VOH Undershoot)
> 2 V at V
CC
= 3.3 V, TA = 25°C
D
Power Off Disables Outputs, Permitting
Live Insertion
D
Support Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V
CC
)
D
ESD Protection Exceeds 2000 V Per
MIL-STD-833, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW)
Packages, and Ceramic Chip Carriers (FK)
description
The SN54LVC646A octal bus transceiver and
register is designed for 2.7-V to 3.6-V V
CC
operation and the SN74LVC646A octal bus
transceiver and register is designed for 1.65-V to
3.6-V V
CC
operation.
These devices consist of bus-transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
input bus or from the internal registers. Data on
the A or B bus is clocked into the registers on the
low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
are performed with the ’LVC646A.
Output-enable (OE
) and direction-control (DIR) inputs control the transceiver functions. In the transceiver
mode, data present at the high-impedance port is stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR
determines which bus receives data when OE
is low. In the isolation mode (OE high), A data is stored in one
register and B data can be stored in the other register.
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
SN74LVC646A. . . DB, DW, OR PW PACKAGE
(TOP VIEW)
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
432128
12 13 14 15 16
OE
B1
B2
NC
B3
B4
B5
A1
A2
A3
NC
A4
A5
A6
SN54LVC646A. . . FK PACKAGE
(TOP VIEW)
DIR
SAB
CLKAB
B8
B7
A8
GND
NC
NC
CLKBA
SBA
V
A7
B6
17 18
27 26
CC
NC – No internal connection
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS302G – JANUARY 1993 – REVISED JUNE1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54L VC646A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVC646A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
DATA I/O
OE
DIR CLKAB CLKBA SAB SBA A1–A8 B1–B8
OPERATION OR FUNCTION
X X ↑ X X X Input Unspecified
†
Store A, B unspecified
†
X XX ↑X X Unspecified
†
Input Store B, A unspecified
†
H X ↑ ↑ X X Input Input Store A and B data
H X H or L H or L X X Input disabled Input disabled Isolation, hold storage
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
L H X X L X Input Output Real-time A data to B bus
L H H or L X H X Input Output Stored A data to B bus
†
The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS302G – JANUARY 1993 – REVISED JUNE1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
L
3
DIR
L
1
CLKAB
X
23
CLKBA
X
2
SAB
X
22
SBA
L
21
L
3
DIR
H
1
CLKAB
X
23
CLKBA
X
2
SAB
L
22
SBA
X
21
X
3
DIR
X
1
CLKAB23CLKBA
X
2
SAB
X
22
SBA
X
21
L
3
DIR
L
1
CLKAB
X
23
CLKBA
H or L
2
SAB
X
22
SBA
H
X
H
X
X
XX
X
X
X
L H H or L X H X
↑
↑
↑↑
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OE OE
OEOE
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS302G – JANUARY 1993 – REVISED JUNE1998
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, and PW packages.
A1
4
B1
20
4D
5
7
7
5
1
1
6D ≥1
≥1
1
2
A2
5
B2
19
A3
6
B3
18
A4
7
B4
17
A5
8
B5
16
A6
9
B6
15
A7
10
B7
14
A8
11
B8
13
OE
G3
21
3 EN2 [AB]
G5
22
SBA
3 EN1 [BA]
3
DIR
23
CLKBA
1
CLKAB
G7
2
SAB
C6
C4
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