Texas Instruments SN74LVC543ADBLE, SN74LVC543ADBR, SN74LVC543ADW, SN74LVC543ADWR, SN74LVC543APWLE Datasheet
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SN74LVC543A
OCTAL REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS299F – JANUARY 1993 – REVISED JUNE 1998
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Typical V
< 0.8 V at V
D
Typical V
> 2 V at V
D
Power Off Disables Outputs, Permitting
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
(Output VOH Undershoot)
OHV
= 3.3 V, TA = 25°C
CC
Live Insertion
D
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V
D
Latch-Up Performance Exceeds 250 mA Per
CC
)
JESD 17
D
Package Options Include Plastic
DB, DW, OR PW PACKAGE
(TOP VIEW)
LEBA
OEBA
A1
A2
A3
A4
A5
A6
A7
A8
CEAB
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
CEBA
B1
B2
B3
B4
B5
B6
B7
B8
LEAB
OEAB
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
description
This octal registered transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74L VC543A contains two sets of D-type latches for temporary storage of data flowing in either direction.
Separate latch-enable (LEAB
register to permit independent control in either direction of data flow.
or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each
The A-to-B enable (CEAB
LEAB
is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB places the A
latches in the storage mode. With CEAB
data present at the output of the A latches. Data flow for B to A is similar to that of A to B, but uses CEBA
and OEBA
.
T o ensure the high-impedance state during power up or power down, OE
) input must be low to enter data from A or to output data from B. If CEAB is low and
and OEAB both low, the 3-state B outputs are active and reflect the
, LEBA,
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
The SN74LVC543A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
1
SN74LVC543A
OCTAL REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS299F – JANUARY 1993 – REVISED JUNE 1998
logic symbol
FUNCTION TABLE
INPUTS
CEAB LEAB OEAB A
H X X X Z
X XHX Z
L HLXB
L LLL L
LLLH H
†
A-to-B data flow is shown; B-to-A flow control is the
same except that it uses CEBA
‡
Output level before the indicated steady-state
input conditions were established
†
OUTPUT
B
‡
0
, LEBA, and OEBA.
§
A1
A2
A3
A4
A5
A6
A7
A8
2
23
1
13
11
14
3
4
5
6
7
8
9
10
1EN3
G1
1C5
2EN4
G2
2C6
3
6D
1
5D
1
4
22
21
20
19
18
17
16
15
B1
B2
B3
B4
B5
B6
B7
B8
OEBA
CEBA
LEBA
OEAB
CEAB
LEAB
§
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
SN74LVC543A
OCTAL REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS299F – JANUARY 1993 – REVISED JUNE 1998
A1
2
23
1
13
11
14
3
C1
1D
To Seven Other Channels
C1
1D
22
B1
OEBA
CEBA
LEBA
OEAB
CEAB
LEAB
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in the high-impedance or power-off state, V
–0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
: (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
O
(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3): DB package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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