TEXAS INSTRUMENTS SN54LVC541A, SN74LVC541A Technical data

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1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

OE1

A1
A2
A3
A4
A5
A6
A7
A8

GND

V

CC

OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8

SN54LVC541A . . . J OR W PACKAGE

SN74LVC541A . . . DB, DGV, DW, NS,

OR PW PACKAGE

(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

4
5
6
7
8

18
17
16
15
14

Y1
Y2
Y3
Y4
Y5

A3
A4
A5
A6
A7

SN54LVC541A. . . FK PACKAGE

(TOP VIEW)

A2A1OE1

Y7

Y6 OE2

A8

GND

Y8

V

CC

SN74LVC541A . . . RGY PACKAGE

(TOP VIEW)

1 20

10 11

2
3
4
5
6
7
8
9

19
18
17
16
15
14
13
12

OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7

A1
A2
A3
A4
A5
A6
A7
A8

OE1Y8V

GND

CC

SN54LVC541A, SN74LVC541A

OCTAL BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCAS298M – JANUARY 1993 – REVISED MAY 2005

FEATURES

• Operate From 1.65 V to 3.6 V

• Inputs Accept Voltages to 5.5 V

• Max tpdof 5.1 ns at 3.3 V

• Typical V

at V

CC

• Typical V

V

= 3.3 V, T

CC

• Support Mixed-Mode Signal Operation on All

Ports (5-V Input/Output Voltage With

3.3-V V

(Output Ground Bounce) < 0.8 V

OLP

= 3.3 V, T

OHV

)

CC

= 25°C

A

(Output V

= 25°C – 1000-V Charged-Device Model (C101)

A

Undershoot) > 2 V at

OH

• I

Supports Partial-Power-Down Mode

off

Operation

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)

ABC

DESCRIPTION/ORDERING INFORMATION

The SN54LVC541A octal buffer/driver is designed for 2.7-V to 3.6-V V
buffer/driver is designed for 1.65-V to 3.6-V V

T

A

–40°C to 85°C SSOP – DB Reel of 2000 SN74LVC541ADBR LC541A

–55°C to 125°C CFP – W Tube of 85 SNJ54LVC541AW SNJ54LVC541AW

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

operation, and the SN74LVC541A octal

operation.

CC

CC

ORDERING INFORMATION

PACKAGE

QFN – RGY Reel of 1000 SN74LVC541ARGYR LC541A

SOIC – DW LVC541A

SOP – NS Reel of 2000 SN74LVC541ANSR LVC541A

TSSOP – PW Reel of 2000 SN74LVC541APWR LC541A

TVSOP – DGV Reel of 2000 SN74LVC541ADGVR LC541A
CDIP – J Tube of 20 SNJ54LVC541AJ SNJ54LVC541AJ

LCCC – FK Tube of 55 SNJ54LVC541AFK SNJ54LVC541AFK

(1)

Tube of 25 SN74LVC541ADW
Reel of 2000 SN74LVC541ADWR

Tube of 70 SN74LVC541APW

Reel of 250 SN74LVC541APWT

ORDERABLE PART NUMBER TOP-SIDE MARKING

Copyright © 1993–2005, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

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OE1
OE2

To Seven Other Channels

A1

Y1

1
19

2 18

SN54LVC541A, SN74LVC541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCAS298M – JANUARY 1993 – REVISED MAY 2005

DESCRIPTION/ORDERING INFORMATION (CONTINUED)

The 'LVC541A devices are ideal for driving bus lines or buffering memory address registers.
These devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board

layout.
The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output enable ( OE1 or OE2)

input is high, all eight outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.
These devices are fully specified for partial-power-down applications using I

outputs, preventing damaging current backflow through the devices when they are powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to V

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

FUNCTION TABLE

INPUTS

OE1 OE2 A

L L L L

L L H H
H X X Z
X H X Z

OUTPUT

Y

. The I

off

circuitry disables the

off

through a pullup

CC

LOGIC DIAGRAM (POSITIVE LOGIC)

2

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SN54LVC541A, SN74LVC541A

OCTAL BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCAS298M – JANUARY 1993 – REVISED MAY 2005

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

V
V
V
V
I

IK

I

OK

I

O

θ

JA

T

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of V
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) The package thermal impedance is calculated in accordance with JESD 51-5.

Supply voltage range –0.5 6.5 V

CC

Input voltage range

I

Voltage range applied to any output in the high-impedance or power-off state

O

Voltage range applied to any output in the high or low state

O

(2)

Input clamp current VI< 0 –50 mA
Output clamp current VO< 0 –50 mA
Continuous output current ±50 mA
Continuous current through V

Package thermal impedance °C/W

Storage temperature range –65 150 °C

stg

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

is provided in the recommended operating conditions table.

CC

(1)

MIN MAX UNIT

–0.5 6.5 V

(2)

(2) (3)

or GND ±100 mA

CC

DB package
DGV package
DW package
NS package
PW package
RGY package

(4)

(4)

(4)

(4)

(4)

(5)

–0.5 6.5 V
–0.5 V

CC

+ 0.5 V

70
92
58
60
83
37

3

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SN54LVC541A, SN74LVC541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCAS298M – JANUARY 1993 – REVISED MAY 2005

Recommended Operating Conditions

V

V

V

V

V

I

OH

I

OL

T

(1) All unused inputs of the device must be held at V

Supply voltage V

CC

High-level input voltage V

IH

Low-level input voltage V

IL

Input voltage 0 5.5 0 5.5 V

I

Output voltage V

O

High-level output current mA

Low-level output current mA

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

(1)

SN54LVC541A SN74LVC541A

MIN MAX MIN MAX

Operating 2 3.6 1.65 3.6
Data retention only 1.5 1.5
V

= 1.65 V to 1.95 V 0.65 × V

CC

= 2.3 V to 2.7 V 1.7 V

CC

V

= 2.7 V to 3.6 V 2 2

CC

V

= 1.65 V to 1.95 V 0.35 × V

CC

= 2.3 V to 2.7 V 0.7 V

CC

V

= 2.7 V to 3.6 V 0.8 0.8

CC

High or low state 0 V

CC

CC

0 V
3-state 0 5.5 0 5.5
V

= 1.65 V –4

CC

V

= 2.3 V –8

CC

V

= 2.7 V –12 –12

CC

V

= 3 V –24 –24

CC

V

= 1.65 V 4

CC

V

= 2.3 V 8

CC

V

= 2.7 V 12 12

CC

V

= 3 V 24 24

CC

or GND to ensure proper device operation. Refer to the TI application report,

CC

UNIT

CC

CC

4

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Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS V

IOH= –100 µ A

IOH= –4 mA 1.65 V 1.2

V

OH

IOH= –8 mA 2.3 V 1.7 V

IOH= –12 mA

IOH= –24 mA 3 V 2.2 2.2

IOL= 100 µ A

V

OL

IOL= 4 mA 1.65 V 0.45
IOL= 8 mA 2.3 V 0.7
IOL= 12 mA 2.7 V 0.4 0.4
IOL= 24 mA 3 V 0.55 0.55

I

I

I

off

I

OZ

I

CC

∆ I

CC

C

i

C

o

(1) All typical values are at V
(2) This applies in the disabled state only.

VI= 0 to 5.5 V 3.6 V ±5 ±5 µ A
VIor VO= 5.5 V 0 ±10 µ A
VO= 0 to 5.5 V 3.6 V ±15 ±10 µ A
VI= V

3.6 V ≤ VI≤ 5.5 V
One input at V

Other inputs at V
VI= V
VO= V

or GND 10 10

CC

CC

CC

or GND 3.3 V 4 4 pF

CC

or GND 3.3 V 5.5 5.5 pF

CC

= 3.3 V, TA= 25°C.

CC

IO= 0 3.6 V µ A

(2)

– 0.6 V,

or GND

CC

1.65 V to 3.6 V V

2.7 V to 3.6 V V

2.7 V 2.2 2.2
3 V 2.4 2.4

1.65 V to 3.6 V 0.2

2.7 V to 3.6 V 0.2

2.7 V to 3.6 V 500 500 µ A

SN54LVC541A SN74LVC541A

MIN TYP

– 0.2

CC

SN54LVC541A, SN74LVC541A

OCTAL BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCAS298M – JANUARY 1993 – REVISED MAY 2005

(1)

MAX MIN TYP

– 0.2

CC

10 10

(1)

UNIT

MAX

V

Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )

PARAMETER V

t

pd

t

en

t

dis

FROM TO V

(INPUT) (OUTPUT) ± 0.3 V

CC

MIN MAX MIN MAX

A Y 5.6 1 5.1 ns
OE Y 7.5 1 7 ns
OE Y 7.7 1 7 ns

SN54LVC541A

= 3.3 V

= 2.7 V UNIT

CC

5

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SN54LVC541A, SN74LVC541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCAS298M – JANUARY 1993 – REVISED MAY 2005

Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )

SN74LVC541A

PARAMETER V

t

pd

t

en

t

dis

t

sk(o)

FROM TO V

(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V

A Y 1 15.7 1 7.8 1 5.6 1.5 5.1 ns
OE Y 1 17.5 1 10.5 1 7.5 1.5 7 ns
OE Y 1 16.5 1 9 1 7.7 1.5 7 ns

Operating Characteristics

TA= 25°C

PARAMETER UNIT

Power dissipation capacitance

C

pd

per buffer/driver

Outputs enabled 65 58 33
Outputs disabled 2 2 2

= 1.8 V V

CC

MIN MAX MIN MAX MIN MAX MIN MAX

TEST

CONDITIONS

f = 10 MHz pF

= 2.5 V V

CC

V

= 1.8 V V

CC

TYP TYP TYP

= 2.7 V UNIT

CC

= 2.5 V V

CC

= 3.3 V

CC

1 ns

= 3.3 V

CC

6

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V

M

t

h

t

su

From Output

Under Test

C

L

(see Note A)

LOAD CIRCUIT

S1

V

LOAD

Open

GND

R

L

R

L

Data Input

Timing Input

V

I

0 V

V

I

0 V

0 V

t

w

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

t

PLH

t

PHL

t

PHL

t

PLH

V

OH

V

OH

V

OL

V

OL

V

I

0 V

Input

Output
Waveform 1
S1 at V

LOAD

(see Note B)

Output
Waveform 2

S1 at GND

(see Note B)

V

OL

V

OH

t

PZL

t

PZH

t

PLZ

t

PHZ

V

LOAD

/2

0 V

VOL + V

∆

VOH − V

∆

≈0 V

V

I

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

V

LOAD

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. t

PLZ

and t

PHZ

are the same as t

dis

.

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

and t

PHL

are the same as tpd.

H. All parameters and waveforms are not applicable to all devices.

Output

Control

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

I

V

M

V

M

1.8 V ± 0.15 V

2.5 V ± 0.2 V

2.7 V

3.3 V ± 0.3 V

1 kΩ
500 Ω
500 Ω
500 Ω

V

CC

R

L

2 × V

CC

2 × V

CC

6 V
6 V

V

LOAD

C

L

30 pF
30 pF
50 pF
50 pF

0.15 V

0.15 V

0.3 V

0.3 V

V

∆

V

CC

V

CC

2.7 V

2.7 V

V

I

VCC/2
VCC/2

1.5 V

1.5 V

V

M

tr/t

f

≤2 ns

≤2 ns
≤2.5 ns
≤2.5 ns

INPUTS

SN54LVC541A, SN74LVC541A

OCTAL BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCAS298M – JANUARY 1993 – REVISED MAY 2005

PARAMETER MEASUREMENT INFORMATION

Figure 1. Load Circuit and Voltage Waveforms

7

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

5962-9759501Q2A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC
5962-9759501QRA ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC
5962-9759501QSA ACTIVE CFP W 20 1 TBD Call TI Level-NC-NC-NC

SN74LVC541ADBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI

SN74LVC541ADBR ACTIVE SSOP DB 20 2000 Pb-Free

SN74LVC541ADBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS &

SN74LVC541ADGVR ACTIVE TVSOP DGV 20 2000 Pb-Free

SN74LVC541ADGVRE4 ACTIVE TVSOP DGV 20 2000 Pb-Free

SN74LVC541ADW ACTIVE SOIC DW 20 25 Pb-Free

SN74LVC541ADWE4 ACTIVE SOIC DW 20 25 Pb-Free

SN74LVC541ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS &

SN74LVC541ADWR ACTIVE SOIC DW 20 2000 Pb-Free

SN74LVC541ADWRE4 ACTIVE SOIC DW 20 2000 Pb-Free

SN74LVC541ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &

SN74LVC541ANSR ACTIVE SO NS 20 2000 Pb-Free

SN74LVC541ANSRE4 ACTIVE SO NS 20 2000 Pb-Free

SN74LVC541ANSRG4 ACTIVE SO NS 20 2000 Green (RoHS &

SN74LVC541APW ACTIVE TSSOP PW 20 70 Pb-Free

SN74LVC541APWE4 ACTIVE TSSOP PW 20 70 Pb-Free

SN74LVC541APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS &

SN74LVC541APWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI

SN74LVC541APWR ACTIVE TSSOP PW 20 2000 Pb-Free

SN74LVC541APWRE4 ACTIVE TSSOP PW 20 2000 Pb-Free

SN74LVC541APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS &

SN74LVC541APWT ACTIVE TSSOP PW 20 250 Pb-Free

SN74LVC541APWTE4 ACTIVE TSSOP PW 20 250 Pb-Free

SN74LVC541ARGYR ACTIVE QFN RGY 20 1000 Green (RoHS &

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-2-260C-1 YEAR/

CU NIPDAU Level-2-260C-1YEAR

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-2-250C-1 YEAR/

CU NIPDAU Level-2-250C-1 YEAR/

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-2-250C-1 YEAR/

CU NIPDAU Level-2-250C-1 YEAR/

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR/

CU NIPDAU Level-2-260C-1 YEAR/

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-2-260C-1YEAR

Level-1-235C-UNLIM

Level-1-235C-UNLIM

Level-1-235C-UNLIM

Level-1-235C-UNLIM

Level-1-235C-UNLIM

Level-1-235C-UNLIM

Level-1-235C-UNLIM

14-Jun-2005

(3)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

14-Jun-2005

(3)

SNJ54LVC541AFK ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC

SNJ54LVC541AJ ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC

SNJ54LVC541AW ACTIVE CFP W 20 1 TBD Call TI Level-NC-NC-NC

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A SQ

B SQ

20

22

23

24

25

19

21

12826 27

12

1314151618 17

0.020 (0,51)

0.010 (0,25)

MIN

0.342

(8,69)

0.442

0.640

0.739

0.938

1.141

A

0.358
(9,09)

0.458

(11,63)

0.660

(16,76)

0.761

(19,32)(18,78)

0.962

(24,43)

1.165

(29,59)

NO. OF

TERMINALS

**

11

10

9

8

7

6

5

432

20

28

44

52

68

84

0.020 (0,51)

0.010 (0,25)

(11,23)

(16,26)

(23,83)

(28,99)

MINMAX

0.307
(7,80)

0.406

(10,31)

0.495

(12,58)

0.495

(12,58)

0.850
(21,6)

1.047
(26,6)

0.080 (2,03)

0.064 (1,63)

B

MAX

0.358
(9,09)

0.458

(11,63)

0.560

(14,22)

0.560

(14,22)

0.858
(21,8)

1.063
(27,0)

0.055 (1,40)

0.045 (1,14)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

4040140/D 10/96

MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,40

24

112

A

0,23
0,13

13

0,07

4,50
4,30

M

6,60
6,20

0,16 NOM

Gage Plane

0,25

0°–8°

0,75
0,50

1,20 MAX

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194

0,15
0,05

14

3,70

3,50

Seating Plane

3,50

20

5,10

4,90

0,08

5,103,70

4,90

382416

7,90

7,70

48

9,80

9,60

56

11,40

11,20

4073251/E 08/00

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,65

28

1

2,00 MAX

0,38
0,22

15

14

A

0,05 MIN

0,15

5,60
5,00

M

8,20
7,40

Seating Plane

0,10

0,25
0,09

0°–ā8°

Gage Plane

0,25

0,95
0,55

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

14

6,50

6,50

5,905,90

2016

7,50

6,90

24

8,50

28

10,50

9,907,90

30

10,50

9,90

38

12,90

12,30

4040065 /E 12/01

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

14

0,30
0,19

8

4,50
4,30

PINS **

7

Seating Plane

0,15
0,05

8

1

A

DIM

6,60
6,20

14

0,10

M

0,10

0,15 NOM

0°–8°

2016

Gage Plane

24

0,25

0,75
0,50

28

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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