TEXAS INSTRUMENTS SN74LVC2G74 Technical data
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DCT OR DCU PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
CLK
D
Q
GND
V
CC
PRE
CLR
Q
4
3
2
1
5
6
7
8
GND
Q
D
CLK
Q
CLR
PRE
V
CC
YEA, YEP, YZA, OR YZP PACKAGE
(BOTTOM VIEW)
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FEATURES
• Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
• Supports 5-V V
• Inputs Accept Voltages to 5.5 V
• Max tpdof 5.9 ns at 3.3 V
• Low Power Consumption, 10- µ A Max I
• ± 24-mA Output Drive at 3.3 V
• Typical V
<0.8 V at V
• Typical V
>2 V at V
• I
off
OLP
CC
OHV
CC
Supports Partial-Power-Down Mode
Operation
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
CC
(Output Ground Bounce)
= 3.3 V, T
(Output V
= 3.3 V, T
Operation
= 25 ° C
A
Undershoot)
OH
= 25 ° C
A
SN74LVC2G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES203K – APRIL 1999 – REVISED JUNE 2005
CC
DESCRIPTION/ORDERING INFORMATION
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V V
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
T
A
–40°C to 85°C
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
operation.
CC
ORDERING INFORMATION
PACKAGE
NanoStar™
WCSP (DSBGA) – YEA
NanoFree™
WCSP (DSBGA) – YZA (Pb-free)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SSOP – DCT Reel of 3000 SN74LVC2G74DCTR C74_ _ _
VSSOP – DCU C74_
(1)
Reel of 3000 _ _ _CP_
Reel of 3000 SN74LVC2G74DCUR
Reel of 250 SN74LVC2G74DCUT
ORDERABLE PART NUMBER TOP-SIDE MARKING
SN74LVC2G74YEAR
SN74LVC2G74YZAR
SN74LVC2G74YEPR
SN74LVC2G74YZPR
(2)
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 1999–2005, Texas Instruments Incorporated
www.ti.com
TG
C
C
TG
C
C
TG
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
Q
C
7
2
6
5
3
1
SN74LVC2G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES203K – APRIL 1999 – REVISED JUNE 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
A low level at the preset ( PRE) or clear ( CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using I
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
H L X X L H
L L X X H
H H ↑ H H L
H H ↑ L L H
H H L X Q
. The I
off
circuitry disables the outputs,
off
(1)
0
(1)
H
Q
0
(1) This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive
(high) level.
LOGIC DIAGRAM (POSITIVE LOGIC)
2
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SN74LVC2G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES203K – APRIL 1999 – REVISED JUNE 2005
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
V
Supply voltage range –0.5 6.5 V
CC
V
Input voltage range
I
V
Voltage range applied to any output in the high-impedance or power-off state
O
V
Voltage range applied to any output in the high or low state
O
I
Input clamp current VI< 0 –50 mA
IK
I
Output clamp current VO< 0 –50 mA
OK
I
Continuous output current ±50 mA
O
Continuous current through V
θ
Package thermal impedance
JA
T
Storage temperature range –65 150 °C
stg
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The value of V
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(2)
is provided in the recommended operating conditions table.
CC
(1)
MIN MAX UNIT
–0.5 6.5 V
(2)
(2) (3)
or GND ±100 mA
CC
–0.5 6.5 V
–0.5 V
DCT package 220
(4)
DCU package 227
YEA/YZA package 140
YEP/YZP package 102
CC
+ 0.5 V
°C/W
3
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SN74LVC2G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES203K – APRIL 1999 – REVISED JUNE 2005
Recommended Operating Conditions
V
V
V
V
V
I
OH
I
OL
∆ t/ ∆ v Input transition rise or fall rate V
T
(1) All unused inputs of the device must be held at V
Supply voltage V
CC
High-level input voltage V
IH
Low-level input voltage V
IL
Input voltage 0 5.5 V
I
Output voltage 0 V
O
High-level output current –16 mA
Low-level output current 16 mA
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(1)
or GND to ensure proper device operation. Refer to the TI application report,
CC
MIN MAX UNIT
Operating 1.65 5.5
Data retention only 1.5
V
= 1.65 V to 1.95 V 0.65 × V
CC
V
= 2.3 V to 2.7 V 1.7
CC
V
= 3 V to 3.6 V 2
CC
V
= 4.5 V to 5.5 V 0.7 × V
CC
V
= 1.65 V to 1.95 V 0.35 × V
CC
V
= 2.3 V to 2.7 V 0.7
CC
V
= 3 V to 3.6 V 0.8
CC
V
= 4.5 V to 5.5 V 0.3 × V
CC
V
= 1.65 V –4
CC
V
= 2.3 V –8
CC
V
= 3 V
CC
V
= 4.5 V –32
CC
V
= 1.65 V 4
CC
V
= 2.3 V 8
CC
V
= 3 V
CC
V
= 4.5 V 32
CC
V
= 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
CC
= 3.3 V ± 0.3 V 10 ns/V
CC
V
= 5 V ± 0.5 V 5
CC
CC
CC
CC
CC
V
CC
–24
24
4
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SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
IOH= –100 µ A 1.65 V to 5.5 V V
IOH= –4 mA 1.65 V 1.2
V
OH
V
OL
Data or
I
I
control inputs
I
off
I
CC
∆ I
CC
C
i
(1) All typical values are at V
IOH= –8 mA 2.3 V 1.9
IOH= –16 mA 2.4
IOH= –24 mA 2.3
IOH= –32 mA 4.5 V 3.8
IOL= 100 µ A 1.65 V to 5.5 V 0.1
IOL= 4 mA 1.65 V 0.45
IOL= 8 mA 2.3 V 0.3
IOL= 16 mA 0.4
IOL= 24 mA 0.55
IOL= 32 mA 4.5 V 0.55
VI= 5.5 V or GND 0 to 5.5 V ±5 µ A
VIor VO= 5.5 V 0 ±10 µ A
VI= 5.5 V or GND, IO= 0 1.65 V to 5.5 V 10 µ A
One input at V
VI= V
CC
= 3.3 V, TA= 25°C.
CC
– 0.6 V, Other inputs at V
CC
or GND 3 V to 5.5 V 500 µ A
CC
or GND 3.3 V 5 pF
WITH CLEAR AND PRESET
SCES203K – APRIL 1999 – REVISED JUNE 2005
CC
3 V
3 V
MIN TYP
– 0.1
CC
SN74LVC2G74
(1)
MAX UNIT
V
V
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )
V
= 1.8 V V
CC
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
f
clock
t
Pulse duration ns
w
t
Setup time, before CLK ↑ ns
su
t
Hold time, data after CLK ↑ 0 0.3 1.2 0.5 ns
h
CLK 6.2 2.7 2.7 2
PRE or CLR low 6.2 2.7 2.7 2
Data 2.9 1.7 1.3 1.1
PRE or CLR inactive 1.9 1.4 1.2 1
80 175 175 200 MHz
= 2.5 V V
CC
= 3.3 V V
CC
CC
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )
V
= 1.8 V V
PARAMETER UNIT
f
max
t
pd
FROM TO
(INPUT) (OUTPUT)
CLK
Q 4.8 13.4 2.2 7.1 2.2 5.9 1.4 4.1
Q 6 14.4 3 7.7 2.6 6.2 1.6 4.4 ns
CC
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
80 175 175 200 MHz
PRE or CLR Q or Q 4.4 12.9 2.3 7 1.7 5.9 1.6 4.1
= 2.5 V V
CC
= 3.3 V V
CC
CC
= 5 V
UNIT
= 5 V
5
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