TEXAS INSTRUMENTS SN74LVC2G125 Technical data

40 C to 85 C

VSSOP

DCU

C25

SN74LVC2G125

DUAL BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SCES204I – APRIL 1999 – REVISED JANUARY 2003

D

Available in the Texas Instruments
NanoStar and NanoFree Packages

D

Supports 5-V VCC Operation

D

Inputs Accept Voltages to 5.5 V

D

Max tpd of 4.3 ns at 3.3 V

D

Low Power Consumption, 10-µA Max I

D

±24-mA Output Drive at 3.3 V

D

Typical V
<0.8 V at V

D

Typical V
>2 V at V

D

I

off

Supports Partial-Power-Down Mode

(Output Ground Bounce)

OLP

= 3.3 V, TA = 25°C

CC

(Output VOH Undershoot)

OHV

= 3.3 V, TA = 25°C

CC

CC

Operation

D

Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II

D

ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)

description/ordering information

This dual bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.

DCT OR DCU PACKAGE

(TOP VIEW)

1OE

1

1A

2

2Y

3

GND

4

YEA OR YZA PACKAGE

(BOTTOM VIEW)

2Y
1A

4
3
2
1

GND

1OE

V

8

2OE

7

1Y

6

2A

5

5

2A

6

1Y

7

2OE

8

V

CC

CC

The SN74LVC2G125 features dual line drivers with 3-state outputs. The outputs are disabled when the
associated output-enable (OE

) input is high.

NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the
die as the package.

ORDERING INFORMA TION

T

A

NanoStar
WCSP (DSBGA) – YEA

NanoFree

–

°

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.

‡

DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.

WCSP (DSBGA) – YZA (Pb-free)

°

SSOP – DCT Reel of 3000 SN74LVC2G125DCTR C25_ _ _

–

PACKAGE

†

Reel of 3000 SN74LVC2G125YEAR

Reel of 3000 SN74LVC2G125YZAR

Reel of 3000 SN74LVC2G125DCUR
Reel of 250 SN74LVC2G125DCUT

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

_ _ _CM_

_

‡

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoStar and NanoFree are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2003, Texas Instruments Incorporated

1

SN74LVC2G125
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS

SCES204I – APRIL 1999 – REVISED JANUARY 2003

description/ordering information (continued)

T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I

off

. The I

circuitry disables the outputs,

off

preventing damaging current backflow through the device when it is powered down.

FUNCTION TABLE

(each buffer)

INPUTS

OE A

L H H
L LL

H X Z

OUTPUT

Y

logic diagram (positive logic)

1

1OE

26

1A 1Y

7

2OE

53

2A 2Y

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in the high-impedance or power-off state, V

–0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

O

(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or low state, V

(see Notes 1 and 2) –0.5 V to V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ

(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 3): DCT package 220°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

O

CC

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DCU package 227°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

YEA/YZA package 140°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The value of VCC is provided in the recommended operating conditions table.

3. The package thermal impedance is calculated in accordance with JESD 51-7.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

2

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VCCSupply voltage

V

VIHHigh-level input voltage

V

VILLow-level input voltage

V

VOOutput voltage

V

V

3 V

V

3 V

SN74LVC2G125

DUAL BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SCES204I – APRIL 1999 – REVISED JANUARY 2003

recommended operating conditions (see Note 4)

MIN MAX UNIT

pp

p

p

V

I

OH

I

OL

∆t/∆v Input transition rise or fall rate

T

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Input voltage 0 5.5 V

I

p

High-level output current

Low-level output current

Operating free-air temperature –40 85 °C

A

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

Operating 1.65 5.5
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × V
VCC = 2.3 V to 2.7 V 1.7
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × V
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V 0.7
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × V

High or low state 0 V
3-state 0 5.5
VCC = 1.65 V –4
VCC = 2.3 V –8

=

CC

VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8

=

CC

VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V 5

CC

CC

CC

–16
–24

16
24

10

CC

CC

mA

mA

ns/V

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3

SN74LVC2G125

V

V

3 V

V

V

3 V

C

V

V

or GND

3.3 V

pF

(INPUT)

(OUTPUT)

PARAMETER

UNIT

C

d

f

MHz

pF

DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS

SCES204I – APRIL 1999 – REVISED JANUARY 2003

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS V

IOH = –100 mA 1.65 V to 5.5 V VCC–0.1
IOH = –4 mA 1.65 V 1.2

OH

OL

I

A or OE inputs VI = 5.5 V or GND 0 to 5.5 V ±5

I

I

off

I

OZ

I

CC

∆I

CC

Data inputs

i

Control inputs

C

o

†

All typical values are at VCC = 3.3 V, TA = 25°C.

IOH = –8 mA 2.3 V 1.9
IOH = –16 mA

IOH = –24 mA
IOH = –32 mA

IOL = 100 mA 1.65 V to 5.5 V 0.1
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.3
IOL = 16 mA

IOL = 24 mA
IOL = 32 mA

VI or VO = 5.5 V 0 ±10
VO = 0 to 5.5 V 3.6 V 10
VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10
One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500

=

I

CC

VO = VCC or GND 3.3 V 6.5 pF

CC

4.5 V 3.8

4.5 V 0.55

MIN TYP†MAX UNIT

2.4

2.3

0.4

0.55

m

A

m

A

m

A

m

A

m

A

3.5
4

p

switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)

PARAMETER

t

pd

t

en

t

dis

FROM

A
OE
OE

operating characteristics, T

Power dissipation

p

capacitance

Outputs enabled
Outputs disabled

A

= 25°

TO

Y
Y
Y

TEST

CONDITIONS

= 10

VCC = 1.8 V

± 0.15 V

MIN MAX MIN MAX MIN MAX MIN MAX

3.3 9.1 1.5 4.8 1.4 4.3 1 3.7 ns
4 9.9 1.9 5.6 1.2 4.7 1.2 3.8 ns

1.5 11.6 1 5.8 1.4 4.6 1 3.4 ns

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V

VCC = 2.5 V

± 0.2 V

TYP TYP TYP TYP

19 19 20 22

2 2 2 3

VCC = 3.3 V

± 0.3 V

VCC = 5 V

± 0.5 V

UNIT

p

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

From Output

Under Test

(see Note A)

C

L

LOAD CIRCUIT

PARAMETER MEASUREMENT INFORMATION

V

S1

R

L

R

L

LOAD

Open

GND

SN74LVC2G125

DUAL BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SCES204I – APRIL 1999 – REVISED JANUARY 2003

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

V

LOAD

GND

V

CC

1.8 V ± 0.15 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V
5 V ± 0.5 V

t

w

Input

Input

Output

Output

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time with one transition per measurement.
E. t

F. t

G. t

H. All parameters and waveforms are not applicable to all devices.

V

M

VOLTAGE WAVEFORMS

PULSE DURATION

V

M

t

PLH

V

M

t

PHL

V

M

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

PLZ
PZL
PLH

and t
and t
and t

are the same as t

PHZ

are the same as ten.

PZH

are the same as tpd.

PHL

INPUTS

V

I

V

CC

V

CC

3 V

V

CC

V

M

V

M

t

PHL

V

M

t

PLH

V

M

.

dis

tr/t

f

≤2 ns

≤2 ns
≤2.5 ns
≤2.5 ns

V

I

0 V

V

OH

V

OL

V

OH

V

OL

V

0 V

I

V

M

VCC/2
VCC/2

1.5 V

VCC/2

V

LOAD

2 × V

CC

2 × V

CC

6 V

2 × V

CC

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at V

LOAD

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

su

V

V

V

∆

0.15 V

0.15 V

0.3 V

0.3 V

V

M

t

h

V

M

M

M

VOL + V

VOH – V

C

L

30 pF
30 pF
50 pF
50 pF

t

PZL

t

PZH

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

R

L

1 kΩ
500 Ω
500 Ω
500 Ω

t

V

M

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

V

M

VOLTAGE WAVEFORMS

t

PLZ

t

PHZ

V

I

0 V

V

V

M

I

0 V

V

I

0 V

V

/2

LOAD

∆

V

OL

V

OH

∆

≈0 V

Figure 1. Load Circuit and Voltage Waveforms

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5

MECHANICAL DATA

MPDS049B – MAY 1999 – REVISED OCTOBER 2002

DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE

0,65

PIN 1
INDEX AREA

0,30
0,15

8

1

3,15
2,75

5

2,90
2,70

4

1,30 MAX

M

0,13

4,25
3,75

Seating Plane

0,15 NOM

0° – 8°

Gage Plane

0,25

0,60
0,20

0,10
0,00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion
D. Falls within JEDEC MO-187 variation DA.

0,10

4188781/C 09/02

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

MECHANICAL DATA

MPDS050B – FEBRUARY 2000 – REVISED OCTOBER 2002

DCU (R-PDSO-G8) PLASTIC SMALL-OUTLINE P ACKAGE

0,50

85

14

2,10
1,90

0,25
0,17

2,40
2,20

0,90 MAX

M

0,08

3,20
3,00

Seating Plane

0,13 NOM

Gage Plane

0°–6°

0,12

0,35
0,20

0,10
0,00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-187

0,10

4200503/D 09/02

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

MECHANICAL DATA

MXBG002B AUGUST 2001 – REVISED MA Y 2002

YEA (R–XBGA–N8) DIE–SIZE BALL GRID ARRAY

1,95
1,85

0,35 MAX

0,95

A

0,85

B

D

C

B

A

PIN A1 INDEX AREA

0,50

0,25

0,25

0,50

1

8X

2

0,19
0,15

M

0,05
0,05

CA

M

C

1,50

B

0,50 MAX

0,15
0,10

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. NanoStar package configuration.
D. Package complies to JEDEC MO–211 variation EB.
E. This package is tin–lead (SnPb). Refer to the 8 YZA package (drawing 4204151) for lead–free.

0,05

C

SEATING PLANE

C

4203167 – 4/C 04/2002

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1

 

MXBG006A – JANUARY 2002 – REVISED APRIL 2002

YZA (R-XBGA-N8) DIE-SIZE BALL GRID ARRAY

0,35 MAX

0,50 MAX

A

1,95
1,85

0,95
0,85

B

Pin A1 Index Area

0,05

0,50

0,25

D

C

1,50

0,50

BCA

0,19
0,15

0,05
0,05

0,25

M
M

C

B

A

1

C

2

8X

0,15
0,10

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. NanoFree package configuration.
D. Package complies to JEDEC MO-211 variation EB.
E. This package is lead-free. Refer to the 8 YEA package (drawing 4203167) for tin-lead (SnPb).

NanoFree is a trademark of Texas Instruments.

Seating Plane

C

4204151-4/B 03/2002

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1

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