Datasheet SN74LVC244ADBLE, SN74LVC244ADBR, SN74LVC244ADGVR, SN74LVC244ADW, SN74LVC244ADWR Datasheet (Texas Instruments)

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SN74LVC244A
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS414L – NOVEMBER 1992 – REVISED APRIL 1999
D
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Typical V <0.8 V at V
D
T ypical V at V
D
Power Off Disables Outputs, Permitting
= 3.3 V, TA = 25°C
CC
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
(Output VOH Undershoot) >2 V
OHV
Live Insertion
D
Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With
3.3-V V
D
ESD Protection Exceeds 2000 V Per
CC
)
MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per JESD 17
D
Package Options Include Shrink Small-Outline (DB), Plastic Small-Outline (DW), and Thin Shrink Small-Outline (PW) Packages
description
DB, DW, OR PW PACKAGE
(TOP VIEW)
1OE
1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1
GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
V
CC
2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
This octal buffer/line driver is operational at 1.5-V to 3.6-V VCC, but designed specifically for 1.65-V to 3.6-V V
CC
operation. The SN74LVC244A is organized as two 4-bit line drivers with separate output-enable (OE
) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVC244A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
OE A
L H H L LL
HXZ
OUTPUT
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN74LVC244A OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCAS414L – NOVEMBER 1992 – REVISED APRIL 1999
logic symbol
1OE
1A1 1A2 1A3 1A4
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1
2 4 6 8
EN
18 16 14 12
1Y1 1Y2 1Y3 1Y4
2OE
2A1 2A2 2A3 2A4
logic diagram (positive logic)
1
1OE
218
1A1
416
1A2
1Y1
1Y2
2OE
2A1
2A2
19
11 13 15 17
19
11 9
13 7
EN
2Y1
2Y2
9
2Y1
7
2Y2
5
2Y3
3
2Y4
614
1A3
812
1A4
1Y3
1Y4
15 5
2A3
17 3
2A4
2Y3
2Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V Input voltage range, V Voltage range applied to any output in the high-impedance or power-off state, V
(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, V
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I Output clamp current, I Continuous output current, I Continuous current through V Package thermal impedance, θ
Storage temperature range, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
O
O
(VI < 0 ) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
VCCSuppl
oltage
V
VOOutput voltage
V
IOHHigh-level output current
mA
IOLLow-level output current
mA
SN74LVC244A
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS414L – NOVEMBER 1992 – REVISED APRIL 1999
recommended operating conditions (see Note 4)
MIN MAX UNIT
pp
y v
V
V
V
T
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 5.5 V
I
p
p
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
Operating 1.65 3.6 Data retention only 1.5 VCC = 1.65 V to 1.95 V 0.65 × V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 2 VCC = 1.65 V to 1.95 V 0.35 × V VCC = 2.3 V to 2.7 V 0.7 VCC = 2.7 V to 3.6 V 0.8
High or low state 0 V 3 state 0 5.5 VCC = 1.65 V –4 VCC = 2.3 V –8 VCC = 2.7 V –12 VCC = 3 V –24 VCC = 1.65 V 4 VCC = 2.3 V 8 VCC = 2.7 V 12 VCC = 3 V 24
CC
1.7
CC
V
CC
V
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3
SN74LVC244A
V
V
I
mA
I
I
0
3.6 V
A
(INPUT)
(OUTPUT)
PARAMETER
UNIT
C
d
f
pF
OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCAS414L – NOVEMBER 1992 – REVISED APRIL 1999
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS
IOH = –100 µA 1.65 V to 3.6 V VCC–0.2 IOH = –4 mA 1.65 V 1.2
OH
V
OL
I
I
I
off
I
OZ
CC
I
CC
C
i
C
All typical values are at VCC = 3.3 V, TA = 25°C.
This applies in the disabled state only.
o
IOH = –8 mA 2.3 V 1.7
= –12
OH
IOH = –24 mA 3 V 2.2 IOL = 100 µA 1.65 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.7 IOL = 12 mA 2.7 V 0.4 IOL = 24 mA 3 V 0.55 VI = 0 to 5.5 V 3.6 V ±5 µA VI or VO = 5.5 V 0 ±10 µA VO = 0 to 5.5 V 3.6 V ±10 µA VI = VCC or GND
3.6 V VI 5.5 V One input at VCC – 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V 500 µA VI = VCC or GND 3.3 V 4 pF VO = VCC or GND 3.3 V 5.5 pF
V
CC
2.7 V 2.2 3 V 2.4
=
O
MIN TYP†MAX UNIT
V
10
µ
10
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 4)
PARAMETER
t
pd
t
en
t
dis
FROM
A Y 5.75 12 1 7.9 6.9 1.5 5.9 ns
OE OE
operating characteristics, T
Power dissipation capacitance
p
per buffer/driver
TO
Y 6.59 13.1 1 9.6 8.6 1.5 7.6 ns Y 5.7 14.6 1 7.8 6.8 1.5 6.5 ns
= 25°C
A
VCC = 1.5 V VCC = 1.8 V
TYP TYP MIN MAX MIN MAX MIN MAX
TEST
CONDITIONS
Outputs enabled Outputs disabled
= 10 MHz
VCC = 2.5 V
± 0.2 V
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
TYP TYP TYP
VCC = 2.7 V
43 43 44
1 1 2
VCC = 3.3 V
± 0.3 V
UNIT
p
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
From Output
Under Test
CL = 15 pF
(see Note A)
SCAS414L – NOVEMBER 1992 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
= 1.5 V
V
CC
2 × V
Open
GND
CC
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
2 k
2 k
S1
SN74LVC244A
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
Open
2 × V
CC
GND
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.1 V
t
PHZ
VOH – 0.1 V
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
5
SN74LVC244A OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCAS414L – NOVEMBER 1992 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 30 pF
(see Note A)
1 k
1 k
S1
V
2 × V
Open
GND
= 1.8 V
CC
CC
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t are the same as ten. are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 2. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
From Output
Under Test
CL = 30 pF
(see Note A)
SCAS414L – NOVEMBER 1992 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
V
= 2.5 V ± 0.2 V
CC
2 × V
Open
GND
CC
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
500
500
S1
SN74LVC244A
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
Open
2 × V
CC
GND
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
7
SN74LVC244A OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCAS414L – NOVEMBER 1992 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
500
500
V
= 2.7 V AND 3.3 V ± 0.3 V
CC
6 V
S1
Open
GND
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
6 V
GND
Timing
Input
Data
Input
Input
Output
LOAD CIRCUIT
t
su
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
t
PLH
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
t
w
2.7 V
2.7 V
0 V
t
h
2.7 V
1.5 V 0 V
2.7 V
0 V
t
PHL
V
OH
V
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
1.5 V
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.
E. t F. t
G. t
PLZ PZL PLH
and t and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
Figure 4. Load Circuit and Voltage Waveforms
8
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.
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