Texas Instruments SN74LVC1G79DBVR, SN74LVC1G79DCKR Datasheet
SN74LVC1G79
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES220C – APRIL 1999 – REVISED FEBRUARY 2000
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
I
Feature Supports Partial-Power-Down
off
Mode Operation
D
Supports 5-V VCC Operation
D
Package Options Include Plastic
DBV OR DCK PACKAGE
(TOP VIEW)
V
5
Q
4
CLK
GND
D
1
2
3
CC
Small-Outline Transistor (DBV, DCK)
Packages
description
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on
the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related
to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without
affecting the levels at the outputs.
The SN74LVC1G79 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
CLK D
↑ H H
↑ LL
L X Q
OUTPUT
Q
0
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
1
D
2
CLK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D
C
4
Q
PRODUCT PREVIEW
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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Copyright 2000, Texas Instruments Incorporated
1
SN74LVC1G79
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES220C – APRIL 1999 – REVISED FEBRUARY 2000
logic diagram (positive logic)
CLK
C
C
C
D
TG
C
C
TG
C
C
TG
C
C
TG
C
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
PRODUCT PREVIEW
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(see Note 3): DBV package 347°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DCK package 389°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Q
†
2
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VCCSuppl
oltage
V
VIHHigh-level input voltage
V
VILLow-level input voltage
V
V
V
V
V
SN74LVC1G79
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES220C – APRIL 1999 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
MIN MAX UNIT
pp
y v
p
p
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate
T
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Input voltage 0 5.5 V
I
Output voltage 0 V
O
High-level output current
Low-level output current
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
Operating 1.65 5.5
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × V
VCC = 2.3 V to 2.7 V 1.7
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × V
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V 0.7
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × V
VCC = 1.65 V –4
VCC = 2.3 V –8
= 3
CC
VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8
= 3
CC
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V 5
CC
CC
CC
–16
–24
16
24
10
CC
CC
V
mA
mA
ns/V
PRODUCT PREVIEW
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