TEXAS INSTRUMENTS SN74LVC1G04 Technical data
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3
2
4
51
NC V
CC
Y
A
GND
DBV PACKAGE
(TOP VIEW)
YEA, YEP, YZA, OR YZP PACKAGE
(BOTTOM VIEW)
DCK PACKAGE
(TOP VIEW)
3
2
4
51
NC V
CC
Y
A
GND
3
2
4
51
NC
Y
A
GND
DNU
GND
V
CC
Y
A
DRL PACKAGE
(TOP VIEW)
See mechanical drawings for dimensions.
1
423
5
V
CC
DNU − Do not use
YZV PACKAGE
(BOTTOM VIEW)
GND
V
CC
Y
A
312
4
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FEATURES
SN74LVC1G04
SINGLE INVERTER GATE
SCES214S – APRIL 1999 – REVISED OCTOBER 2005
• Available in the Texas Instruments • I
NanoStar™ and NanoFree™ Packages Operation
• Supports 5-V V
Operation • Latch-Up Performance Exceeds 100 mA Per
CC
• Inputs Accept Voltages to 5.5 V
• Max tpdof 3.3 ns at 3.3 V
• Low Power Consumption, 10- µ A Max I
CC
• ESD Protection Exceeds JESD 22
• ± 24-mA Output Drive at 3.3 V
Supports Partial-Power-Down Mode
off
JESD 78, Class II
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This single inverter gate is designed for 1.65-V to 5.5-V V
The SN74LVC1G04 performs the Boolean function Y = A.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I
preventing damaging current backflow through the device when it is powered down.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
operation.
CC
. The I
off
circuitry disables the outputs,
off
Copyright © 1999–2005, Texas Instruments Incorporated
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A Y
2 4
A Y
1 3
SN74LVC1G04
SINGLE INVERTER GATE
SCES214S – APRIL 1999 – REVISED OCTOBER 2005
ORDERING INFORMATION
T
A
NanoStar™ – WCSP (DSBGA)
0.17-mm Small Bump – YEA
NanoFree™ – WCSP (DSBGA)
0.17-mm Small Bump – YZA SN74LVC1G04YZAR
(Pb-free)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP Reel of 3000
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP SN74LVC1G04YZPR
–40 ° C to 85 ° C
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP/YZV: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and
one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
(Pb-free)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YZV SN74LVC1G04YZVR PREVIEW
(Pb-free)
SOT (SOT-23) – DBV C04_
SOT (SC-70) – DCK
SOT (SOT-553) – DRL Reel of 4000 SN74LVC1G04DRLR
PACKAGE
(1)
Reel of 3000 SN74LVC1G04DBVR
Reel of 250 SN74LVC1G04DBVT
Reel of 3000 SN74LVC1G04DCKR
Reel of 250 SN74LVC1G04DCKT CC_
ORDERABLE PART NUMBER TOP-SIDE MARKING
SN74LVC1G04YEAR
_ _ _CC_
SN74LVC1G04YEPR
(2)
FUNCTION TABLE
INPUT OUTPUT
A Y
H L
L H
LOGIC DIAGRAM (POSITIVE LOGIC)
(DBV, DCK, DRL, YEA, YEP, YZA, AND YZP PACKAGE)
LOGIC DIAGRAM (POSITIVE LOGIC)
(YZV PACKAGE)
2
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SN74LVC1G04
SINGLE INVERTER GATE
SCES214S – APRIL 1999 – REVISED OCTOBER 2005
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
V
V
V
V
I
IK
I
OK
I
O
θ
JA
T
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of V
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Supply voltage range –0.5 6.5 V
CC
Input voltage range –0.5 6.5 V
I
Voltage range applied to any output in the high-impedance or power-off state
O
Voltage range applied to any output in the high or low state
O
Input clamp current VI< 0 –50 mA
Output clamp current VO< 0 –50 mA
Continuous output current ± 50 mA
Continuous current through V
Package thermal impedance
Storage temperature range –65 150 ° C
stg
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
is provided in the recommended operating conditions table.
CC
(1)
MIN MAX UNIT
(2)
(2) (3)
or GND ± 100 mA
CC
–0.5 6.5 V
–0.5 V
DBV package 206
DCK package 252
(4)
DRL package 142
YEA/YZA package 154
YEP/YZP package 132
YZV package TBD
CC
+ 0.5 V
° C/W
3
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SN74LVC1G04
SINGLE INVERTER GATE
SCES214S – APRIL 1999 – REVISED OCTOBER 2005
Recommended Operating Conditions
V
V
V
V
V
I
I
∆ t/ ∆ v Input transition rise or fall rate V
T
(1) All unused inputs of the device must be held at V
Supply voltage V
CC
High-level input voltage V
IH
Low-level input voltage V
IL
Input voltage 0 5.5 V
I
Output voltage 0 V
O
High-level output current –16 mA
OH
Low-level output current 16 mA
OL
Operating free-air temperature –40 85 ° C
A
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(1)
or GND to ensure proper device operation. Refer to the TI application report,
CC
MIN MAX UNIT
Operating 1.65 5.5
Data retention only 1.5
V
= 1.65 V to 1.95 V 0.65 × V
CC
V
= 2.3 V to 2.7 V 1.7
CC
V
= 3 V to 3.6 V 2
CC
V
= 4.5 V to 5.5 V 0.7 × V
CC
V
= 1.65 V to 1.95 V 0.35 × V
CC
V
= 2.3 V to 2.7 V 0.7
CC
V
= 3 V to 3.6 V 0.8
CC
V
= 4.5 V to 5.5 V 0.3 × V
CC
V
= 1.65 V –4
CC
V
= 2.3 V –8
CC
V
= 3 V
CC
V
= 4.5 V –32
CC
V
= 1.65 V 4
CC
V
= 2.3 V 8
CC
V
= 3 V
CC
V
= 4.5 V 32
CC
V
= 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
CC
= 3.3 V ± 0.3 V 10 ns/V
CC
V
= 5 V ± 0.5 V 5
CC
CC
CC
CC
CC
V
CC
–24
24
4
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Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
IOH= –100 µ A 1.65 V to 5.5 V V
IOH= –4 mA 1.65 V 1.2
V
OH
V
OL
I
I
I
∆ I
C
A input VI= 5.5 V or GND 0 to 5.5 V ± 5 µ A
I
off
CC
CC
i
(1) All typical values are at V
IOH= –8 mA 2.3 V 1.9
IOH= –16 mA 2.4
IOH= –24 mA 2.3
IOH= –32 mA 4.5 V 3.8
IOL= 100 µ A 1.65 V to 5.5 V 0.1
IOL= 4 mA 1.65 V 0.45
IOL= 8 mA 2.3 V 0.3
IOL= 16 mA 0.4
IOL= 24 mA 0.55
IOL= 32 mA 4.5 V 0.55
VIor VO= 5.5 V 0 ± 10 µ A
VI= 5.5 V or GND IO= 0 1.65 V to 5.5 V 10 µ A
One input at V
VI= V
CC
– 0.6 V, Other inputs at V
CC
or GND 3 V to 5.5 V 500 µ A
CC
or GND 3.3 V 3.5 pF
= 3.3 V, TA= 25 ° C.
CC
SN74LVC1G04
SINGLE INVERTER GATE
SCES214S – APRIL 1999 – REVISED OCTOBER 2005
CC
MIN TYP
– 0.1
CC
3 V
3 V
(1)
MAX UNIT
V
V
Switching Characteristics
over recommended operating free-air temperature range, CL= 15 pF (unless otherwise noted) (see Figure 1 )
V
= 1.8 V V
PARAMETER UNIT
t
pd
FROM TO
(INPUT) (OUTPUT)
A Y 2 6.4 1 4.2 0.7 3.3 0.7 3.1 ns
CC
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
= 2.5 V V
CC
= 3.3 V V
CC
= 5 V
CC
Switching Characteristics
over recommended operating free-air temperature range, CL= 30 pF or 50 pF (unless otherwise noted) (see Figure 2 )
V
= 1.8 V V
PARAMETER UNIT
t
pd
FROM TO
(INPUT) (OUTPUT)
A Y 3 7.5 1.4 5.2 1 4.2 1 3.7 ns
CC
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
= 2.5 V V
CC
= 3.3 V V
CC
= 5 V
CC
Operating Characteristics
TA= 25 ° C
V
= 1.8 V V
PARAMETER UNIT
C
Power dissipation capacitance f = 10 MHz 16 18 18 20 pF
pd
TEST
CONDITIONS
CC
TYP TYP TYP TYP
= 2.5 V V
CC
= 3.3 V V
CC
= 5 V
CC
5
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V
M
t
h
t
su
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
S1
V
LOAD
Open
GND
R
L
R
L
Data Input
Timing Input
V
I
0 V
V
I
0 V
0 V
t
w
Input
VOLTAGE W AVEFORMS
SETUP AND HOLD TIMES
VOLTAGE W AVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE W AVEFORMS
PULSE DURATION
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
V
I
0 V
Input
Output
Waveform 1
S1 at V
LOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
V
LOAD
/2
0 V
VOL + V
∆
VOH − V
∆
≈0 V
V
I
VOLTAGE W AVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
V
LOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low , except when disabled by the output control.
Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
I
V
M
V
M
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
1 MΩ
1 MΩ
1 MΩ
1 MΩ
V
CC
R
L
2 × V
CC
2 × V
CC
6 V
2 × V
CC
V
LOAD
C
L
15 pF
15 pF
15 pF
15 pF
0.15 V
0.15 V
0.3 V
0.3 V
V
∆
V
CC
V
CC
3 V
V
CC
V
I
VCC/2
VCC/2
1.5 V
VCC/2
V
M
tr/t
f
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
SN74LVC1G04
SINGLE INVERTER GATE
SCES214S – APRIL 1999 – REVISED OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION
6
Figure 1. Load Circuit and Voltage Waveforms
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