Texas Instruments SN74LVC16373DGGR, SN74LVC16373DL, SN74LVC16373DLR Datasheet

SN74LVC16373

16-BIT TRANSPARENT D-TYPE LATCH

WITH 3-STATE OUTPUTS

SCAS315B – NOVEMBER 1993 – REVISED JUL Y 1995

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Member of the Texas Instruments

Widebus

 Family

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

T ypical V

OLP

(Output Ground Bounce)

< 0.8 V at VCC = 3.3 V, TA = 25°C

D

T ypical V

OHV

(Output VOH Undershoot)

> 2 V at VCC = 3.3 V, TA = 25°C

D

Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages

description

This 16-bit transparent D-type latch is designed
for 2.7-V to 3.6-V VCC operation.

The SN74LVC16373 is particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers. It
can be used as two 8-bit latches or one 16-bit
latch. When the latch-enable (LE) input is high, the
Q outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the levels
set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly . The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components.

OE

does not affect internal operations of the latch. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVC16373 is characterized for operation from –40°C to 85°C.

Copyright  1995, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

DGG OR DL PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

1OE

1Q1
1Q2

GND

1Q3
1Q4

V

CC

1Q5
1Q6

GND

1Q7
1Q8
2Q1
2Q2

GND

2Q3
2Q4

V

CC

2Q5
2Q6

GND

2Q7
2Q8

2OE

1LE
1D1
1D2
GND
1D3
1D4
V

CC

1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V

CC

2D5
2D6
GND
2D7
2D8
2LE

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN74LVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS

SCAS315B – NOVEMBER 1993 – REVISED JUL Y 1995

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

(each 8-bit section)

INPUTS

OUTPUT

OE

LE D

Q

L H H H
L HL L
L LX Q

0

H X X Z

logic symbol

†

logic diagram (positive logic)

1OE

2OE

48

47

1OE

1

1LE

1D1

To Seven Other Channels

2

1Q1

C1
1D

25

36

2OE

24

2LE

2D1

13

2Q1

C1
1D

To Seven Other Channels

1EN

1

C3

48

1LE

3D

47

1D1

46

1D2

44

1D3

43

1D4

1Q1

2

1Q2

3

1Q3

5

1Q4

6

1

41

1D5

40

1D6

38

1D7

37

1D8

1Q5

8

1Q6

9

1Q7

11

1Q8

12

4D

36

2D1

35

2D2

33

2D3

32

2D4

2Q1

13

2Q2

14

2Q3

16

2Q4

17

30

2D5

29

2D6

27

2D7

26

2D8

2Q5

19

2Q6

20

2Q7

22

2Q8

23

2

2EN

24

C4

25

2LE

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.