Texas Instruments SN74LVC138ADR, SN74LVC138APWLE, SN74LVC138APWR, SN74LVC138AD, SN74LVC138ADBR Datasheet
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SN54LVC138A, SN74LVC138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS291I – MARCH 1993 – REVISED OCTOBER 1998
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Typical V
< 0.8 V at V
D
Typical V
> 2 V at V
D
Inputs Accept Voltages to 5.5 V
D
Package Options Include Plastic
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
(Output VOH Undershoot)
OHV
= 3.3 V, TA = 25°C
CC
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK) and
Flat (W) Package, and DIPs (J)
description
The SN54LVC138A 3-line to 8-line decoder/
demultiplexer is designed for 2.7-V to 3.6-V V
operation and the SN74LVC138A 3-line to 8-line
CC
SN54LVC138A...J OR W PACKAGE
SN74LVC138A. . . D, DB, OR PW PACKAGE
SN54LVC138A. . . FK PACKAGE
C
G
2A
NC
G
2B
G1
(TOP VIEW)
A
1
B
2
C
3
G2A
4
G2B
5
G1
6
Y7
7
GND
8
(TOP VIEW)
BANC
3212019
4
5
6
7
8
910111213
16
15
14
13
12
11
10
9
V
CC
V
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y0
18
17
16
15
14
CC
Y1
Y2
NC
Y3
Y4
decoder/demultiplexer is designed for 1.65-V to
Y6
3.6-V V
operation.
CC
The ’LVC138A devices are designed for highperformance memory-decoding or data-routing
Y7
GND
NC – No internal connection
NC
Y5
applications requiring very short propagation
delay times. In high-performance memory systems, these decoders minimize the effects of system decoding.
When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and
the enable time of the memory are usually less than the typical access time of the memory. This means that
the effective system delay introduced by the decoders is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires
only one inverter. An enable input can be used as a data input for demultiplexing applications.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
The SN54L VC138A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVC138A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54LVC138A, SN74LVC138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS291I – MARCH 1993 – REVISED OCTOBER 1998
FUNCTION TABLE
ENABLE INPUTS
G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X H X X X X H H H H H H H H
X XHXXXHHHHHHHH
LXXXXXHHHHHHHH
HLLLLLLHHHHHHH
HLLLLHHLHHHHHH
HLLLHLHHLHHHHH
HLLLHHHHHLHHHH
HLLHLLHHHHLHHH
HLLHLHHHHHHLHH
HLLHHLHHHHHHLH
HL LHHHHHHHHHHL
SELECT INPUTS OUTPUTS
logic symbols (alternatives)
1
A
2
B
3
C
6
G1
4
G2A
5
G2B
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, PW, and W packages.
BIN/OCT
1
2
4
&
EN
†
15
0
1
2
3
4
5
6
7
14
13
12
11
10
Y0
Y1
Y2
Y3
Y4
Y5
9
Y6
7
Y7
G1
G2A
G2B
1
A
2
B
3
C
6
4
5
DMUX
0
G
2
&
0
0
1
7
2
3
4
5
6
7
15
14
13
12
11
10
Y0
Y1
Y2
Y3
Y4
Y5
9
Y6
7
Y7
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1
A
SN54LVC138A, SN74LVC138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS291I – MARCH 1993 – REVISED OCTOBER 1998
15
Y0
14
Y1
G1
G2A
G2B
2
B
3
C
6
4
5
13
12
11
10
Y2
Y3
Data
Outputs
Y4
Y5
9
Y6
7
Y7
Select
Inputs
Enable
Inputs
Pin numbers shown are for the D, DB, J, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DB package 131°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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