Datasheet SN74LVC112AD, SN74LVC112APWR, SN74LVC112ADBLE, SN74LVC112ADBR, SN74LVC112ADGVR Datasheet (Texas Instruments)
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SN74LVC112A
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SCAS289G – JANUARY 1993 – REVISED SEPTEMBER 1998
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Typical V
< 0.8 V at V
D
Typical V
> 2 V at V
D
Inputs Accept Voltages to 5.5 V
D
Package Options Include Plastic
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
(Output VOH Undershoot)
OHV
= 3.3 V, TA = 25°C
CC
D, DB, DGV, OR PW PACKAGE
1PRE
1CLK
1K
1J
1Q
1Q
2Q
GND
(TOP VIEW)
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
V
CC
1CLR
2CLR
2CLK
2K
2J
2PRE
2Q
Small-Outline (D), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages
description
This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V VCC operation.
A low level at the preset (PRE
other inputs. When PRE
requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the J and K inputs can be changed without affecting the levels at the outputs. The SN74LVC112A can
perform as a toggle flip-flop by tying J and K high.
) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
and CLR are inactive (high), data at the J and K inputs meeting the setup time
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
The SN74LVC112A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
PRE CLR CLK J K Q Q
L H X X X H L
H LXXXLH
LLXXXH
HH↓LLQ
HH↓HLHL
HH↓LHLH
HH↓H H Toggle
H H H X X Q
†
The output levels in this configuration may not meet the
minimum levels for VOH. Furthermore, this configuration is
unstable; that is, it does not persist when either PRE
returns to its inactive (high) level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OUTPUTS
†
H
Q
0
Q
0
or CLR
†
0
0
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
1
SN74LVC112A
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SCAS289G – JANUARY 1993 – REVISED SEPTEMBER 1998
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
1J
1K
2J
2K
4
3
1
2
15
10
11
13
12
14
S
1J
C1
1K
R
1PRE
1CLK
1CLR
2PRE
2CLK
2CLR
logic diagram, each flip-flop (positive logic)
5
1Q
6
1Q
9
2Q
7
2Q
PRE
CLK
Q
K
Q
CLR
J
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VCCSuppl
oltage
V
IOHHigh-level output current
mA
IOLLow-level output current
mA
SN74LVC112A
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SCAS289G – JANUARY 1993 – REVISED SEPTEMBER 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
–0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
†
DB package 131°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 180°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 4)
MIN MAX UNIT
pp
y v
V
V
V
V
∆t/∆v Input transition rise or fall rate 0 10 ns/V
T
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 5.5 V
I
Output voltage 0 V
O
p
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
Operating 1.65 3.6
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V 0.7
VCC = 2.7 V to 3.6 V 0.8
VCC = 1.65 V –4
VCC = 2.3 V –8
VCC = 2.7 V –12
VCC = 3 V –24
VCC = 1.65 V 4
VCC = 2.3 V 8
VCC = 2.7 V 12
VCC = 3 V 24
CC
1.7
CC
V
CC
V
V
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3
SN74LVC112A
V
V
I
mA
tsuSetup time
ns
(INPUT)
(OUTPUT)
t
Q
Q
ns
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SCAS289G – JANUARY 1993 – REVISED SEPTEMBER 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
IOH = –100 µA 1.65 V to 3.6 V VCC–0.2
IOH = –4 mA 1.65 V 1.2
OH
V
OL
I
I
I
CC
∆I
CC
C
†
All typical values are at VCC = 3.3 V, TA = 25°C.
i
IOH = –8 mA 2.3 V 1.7
= –12
OH
IOH = –24 mA 3 V 2.2
IOL = 100 µA 1.65 V to 3.6 V 0.2
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.7
IOL = 12 mA 2.7 V 0.4
IOL = 24 mA 3 V 0.55
VI = 5.5 V or GND 3.6 V ±5 µA
VI = VCC or GND, IO = 0 3.6 V 10 µA
One input at VCC – 0.6 V,
Other inputs at VCC or GND
VI = VCC or GND 3.3 V 4.5 pF
V
CC
2.7 V 2.2
3 V 2.4
2.7 V to 3.6 V 500 µA
MIN TYP†MAX UNIT
V
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
f
clock
t
w
t
h
‡
This information was not available at the time of publication.
Clock frequency
Pulse duration, CLK high or low
p
Hold time, data after CLK↓
Data before CLK↓
PRE or CLR inactive
VCC = 1.8 V
± 0.15 V
MIN MAX MIN MAX MIN MAX MIN MAX
‡ ‡
‡ ‡
‡ ‡
‡ ‡
VCC = 2.5 V
± 0.2 V
‡ ‡
VCC = 2.7 V
3.3 3.3 ns
2.3 3.1
1.1 2.4
0.7 2.5 ns
VCC = 3.3 V
± 0.3 V
150 150 MHz
UNIT
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
f
max
pd
‡
This information was not available at the time of publication.
4
FROM
CLR or PRE
CLK
TO
or
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VCC = 1.8 V
± 0.15 V
MIN MAX MIN MAX MIN MAX MIN TYP MAX
‡ ‡
‡ ‡ ‡ ‡
‡ ‡ ‡ ‡
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V VCC = 3.3 V ± 0.3 V
150 150 MHz
5.5 1 3.4 4.8
7.1 1 3.5 5.9
UNIT
SN74LVC112A
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SCAS289G – JANUARY 1993 – REVISED SEPTEMBER 1998
operating characteristics, T
PARAMETER
C
†
This information was not available at the time of publication.
Power dissipation capacitance per flip-flop f = 10 MHz
pd
= 25°C
A
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 30 pF
(see Note A)
Timing
Input
Data
Input
Input
t
Output
LOAD CIRCUIT
t
su
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
PLH
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1 kΩ
VCC/2
t
h
1 kΩ
S1
VCC/2
TEST CONDITIONS
= 1.8 V ± 0.15 V
V
CC
2 × V
CC
Open
GND
V
CC
0 V
V
CC
0 V
V
CC
0 V
t
PHL
V
OH
V
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VCC = 1.8 V
± 0.15 V
TYP TYP TYP
t
PZL
CC
t
PZH
ENABLE AND DISABLE TIMES
VCC = 2.5 V
± 0.2 V
† †
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
t
w
VOLTAGE WAVEFORMS
PULSE DURATION
VCC/2
VCC/2
VOLTAGE WAVEFORMS
VCC = 3.3 V
Open
2 × V
CC
Open
± 0.3 V
24 pF
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
UNIT
V
CC
0 V
V
CC
0 V
V
CC
V
OL
V
OH
0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74LVC112A
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SCAS289G – JANUARY 1993 – REVISED SEPTEMBER 1998
PARAMETER MEASUREMENT INFORMATION
V
= 2.5 V ± 0.2 V
CC
2 × V
CC
Open
GND
From Output
Under Test
CL = 30 pF
(see Note A)
500 Ω
500 Ω
S1
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 2. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC112A
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SCAS289G – JANUARY 1993 – REVISED SEPTEMBER 1998
PARAMETER MEASUREMENT INFORMATION
V
= 2.7 V AND 3.3 V ± 0.3 V
CC
From Output
Under Test
CL = 50 pF
(see Note A)
Timing
Input
Data
Input
Input
t
PLH
Output
500 Ω
500 Ω
LOAD CIRCUIT
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
h
S1
t
PHL
6 V
GND
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
V
V
Open
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
t
w
t
1.5 V
t
PHZ
1.5 V
Open
6 V
GND
1.5 V1.5 V
PLZ
VOL + 0.3 V
VOH – 0.3 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Figure 3. Load Circuit and Voltage Waveforms
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7
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Copyright 1998, Texas Instruments Incorporated
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