TEXAS INSTRUMENTS SN74LVC112A Technical data

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1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

1CLK

1K

1J

1PRE

1Q
1Q
2Q

GND

V

CC

1CLR
2CLR
2CLK
2K
2J
2PRE
2Q

D, DB, DGV, NS, OR PW PACKAGE

(TOP VIEW)

SN74LVC112A

DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP

WITH CLEAR AND PRESET

SCAS289L – JANUARY 1993 – REVISED AUGUST 2005

FEATURES

• Operates From 1.65 V to 3.6 V

• Inputs Accept Voltages to 5.5 V

• Max tpdof 4.8 ns at 3.3 V

• Typical V

<0.8 V at V

• Typical V

>2 V at V

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V V
A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the

other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time
requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the J and K inputs can be changed without affecting the levels at the outputs. The SN74LVC112A can
perform as a toggle flip-flop by tying J and K high.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.

OLP

CC

OHV

CC

(Output Ground Bounce)

= 3.3 V, T

(Output V

= 3.3 V, T

A

= 25 ° C

A
OH

= 25 ° C

Undershoot)

operation.

CC

T

A

–40 ° C to 85 ° C SSOP – DB Reel of 2000 SN74LVC112ADBR LC112A

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ORDERING INFORMATION

PACKAGE

SOIC – D Reel of 2500 SN74LVC112ADR LVC112A

SOP – NS Reel of 2000 SN74LVC112ANSR LVC112A

TSSOP – PW Reel of 2000 SN74LVC112APWR LC112A

TVSOP – DGV Reel of 2000 SN74LVC112ADGVR LC112A

(1)

Tube of 40 SN74LVC112AD

Reel of 250 SN74LVC112ADT

Tube of 90 SN74LVC112APW

Reel of 250 SN74LVC112APWT

ORDERABLE PART NUMBER TOP-SIDE MARKING

Copyright © 1993–2005, Texas Instruments Incorporated

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PRE

CLK

K

Q

Q

CLR

J

SN74LVC112A
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET

SCAS289L – JANUARY 1993 – REVISED AUGUST 2005

PRE CLR CLK J K Q Q

H L X X X L H

H H ↓ L L Q
H H ↓ H L H L
H H ↓ L H L H
H H ↓ H H Toggle
H H H X X Q

(1) The output levels in this configuration may not meet the minimum

LOGIC DIAGRAM, EACH FLIP-FLOP (POSITIVE LOGIC)

FUNCTION TABLE

INPUTS OUTPUTS

L H X X X H L

L L X X X H

levels for VOH. Furthermore, this configuration is nonstable; that is,
it does not persist when either PRE or CLR returns to its inactive
(high) level.

(1)

0

0

(1)

H

Q

0

Q

0

2

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SN74LVC112A

DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP

WITH CLEAR AND PRESET

SCAS289L – JANUARY 1993 – REVISED AUGUST 2005

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

V

CC

V

I

V

O

I

IK

I

OK

I

O

θ

JA

T

stg

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of V
(4) The package thermal impedance is calculated in accordance with JESD 51-7.

Supply voltage range –0.5 6.5 V
Input voltage range
Output voltage range
Input clamp current VI< 0 –50 mA
Output clamp current VO< 0 –50 mA
Continuous output current ± 50 mA
Continuous current through V

Package thermal impedance

Storage temperature range –65 150 ° C

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

is provided in the recommended operating conditions table.

CC

(1)

MIN MAX UNIT

(2)

(2) (3)

or GND ± 100 mA

CC

–0.5 6.5 V
–0.5 V

+ 0.5 V

CC

D package 73
DB package 82

(4)

DGV package 120 ° C/W
NS package 64
PW package 108

Recommended Operating Conditions

(1)

MIN MAX UNIT

V

V

V

V
V

I

OH

I

OL

Supply voltage V

CC

High-level input voltage V

IH

Low-level input voltage V

IL

Input voltage 0 5.5 V

I

Output voltage 0 V

O

High-level output current mA

Low-level output current mA

Operating 1.65 3.6
Data retention only 1.5
V

= 1.65 V to 1.95 V 0.65 × V

CC

= 2.3 V to 2.7 V 1.7 V

CC

V

= 2.7 V to 3.6 V 2

CC

V

= 1.65 V to 1.95 V 0.35 × V

CC

= 2.3 V to 2.7 V 0.7 V

CC

V

= 2.7 V to 3.6 V 0.8

CC

V

= 1.65 V –4

CC

V

= 2.3 V –8

CC

V

= 2.7 V –12

CC

V

= 3 V –24

CC

V

= 1.65 V 4

CC

V

= 2.3 V 8

CC

V

= 2.7 V 12

CC

V

= 3 V 24

CC

CC

∆ t/ ∆ v Input transition rise or fall rate 10 ns/V
T

(1) All unused inputs of the device must be held at V

Operating free-air temperature –40 85 ° C

A

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

CC

CC

V

CC

3

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SN74LVC112A
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET

SCAS289L – JANUARY 1993 – REVISED AUGUST 2005

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS V

IOH= –100 µ A 1.65 V to 3.6 V V
IOH= –4 mA 1.65 V 1.2

V

OH

V

OL

I

I

I

CC

∆ I

CC

C

i

(1) All typical values are at V

IOH= –8 mA 2.3 V 1.7

IOH= –12 mA

IOH= –24 mA 3 V 2.2
IOL= 100 µ A 1.65 V to 3.6 V 0.2
IOL= 4 mA 1.65 V 0.45
IOL= 8 mA 2.3 V 0.7 V
IOL= 12 mA 2.7 V 0.4
IOL= 24 mA 3 V 0.55
VI= 5.5 V or GND 3.6 V ± 5 µ A
VI= V
One input at V
VI= V

or GND, IO= 0 3.6 V 10 µ A

CC

– 0.6 V, Other inputs at V

CC

or GND 3.3 V 4.5 pF

CC

= 3.3 V, TA= 25 ° C.

CC

or GND 2.7 V to 3.6 V 500 µ A

CC

CC

2.7 V 2.2
3 V 2.4

MIN TYP

– 0.2

CC

(1)

MAX UNIT

V

Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )

V

f

clock

t

w

t

su

t

h

Clock frequency
Pulse duration, CLK high or low

Setup time ns

Hold time, data after CLK ↓

(1) This information was not available at the time of publication.

Data before CLK ↓
PRE or CLR inactive

= 1.8 V V

CC

± 0.15 V ± 0.2 V ± 0.3 V

MIN MAX MIN MAX MIN MAX MIN MAX

(1) (1)
(1) (1)
(1) (1)
(1) (1)
(1) (1)

= 2.5 V V

CC

V

= 2.7 V

CC

3.3 3.3 ns

3.1 2.3

2.4 1.1

2.5 0.7 ns

= 3.3 V

CC

150 150 MHz

Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )

V

= 1.8 V V

PARAMETER UNIT

f

max

t

pd

FROM TO

(INPUT) (OUTPUT)

CLR or PRE

CLK

Q or Q ns

CC

± 0.15 V ± 0.2 V

MIN MAX MIN MAX MIN MAX MIN TYP MAX

(1) (1)
(1) (1) (1) (1)
(1) (1) (1) (1)

(1) This information was not available at the time of publication.

= 2.5 V

CC

V

CC

= 2.7 V V

= 3.3 V ± 0.3 V

CC

150 150 MHz

5.5 1 3.4 4.8

7.1 1 3.5 5.9

UNIT

Operating Characteristics

TA= 25 ° C

PARAMETER TEST CONDITIONS UNIT

C

(1) This information was not available at the time of publication.

4

Power dissipation capacitance f = 10 MHz

pd

V

= 1.8 V V

CC

= 2.5 V V

CC

TYP TYP TYP

(1) (1)

= 3.3 V

CC

24 pF

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V

M

t

h

t

su

From Output

Under Test

C

L

(see Note A)

LOAD CIRCUIT

S1

V

LOAD

Open

GND

R

L

R

L

Data Input

Timing Input

V

I

0 V

V

I

0 V

0 V

t

w

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

t

PLH

t

PHL

t

PHL

t

PLH

V

OH

V

OH

V

OL

V

OL

V

I

0 V

Input

Output
Waveform 1
S1 at V

LOAD

(see Note B)

Output
Waveform 2

S1 at GND

(see Note B)

V

OL

V

OH

t

PZL

t

PZH

t

PLZ

t

PHZ

V

LOAD

/2

0 V

VOL + V

∆

VOH − V

∆

≈0 V

V

I

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

V

LOAD

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. t

PLZ

and t

PHZ

are the same as t

dis

.

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

and t

PHL

are the same as tpd.

H. All parameters and waveforms are not applicable to all devices.

Output

Control

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

I

V

M

V

M

1.8 V ± 0.15 V

2.5 V ± 0.2 V

2.7 V

3.3 V ± 0.3 V

1 kΩ
500 Ω
500 Ω
500 Ω

V

CC

R

L

2 × V

CC

2 × V

CC

6 V
6 V

V

LOAD

C

L

30 pF
30 pF
50 pF
50 pF

0.15 V

0.15 V

0.3 V

0.3 V

V

∆

V

CC

V

CC

2.7 V

2.7 V

V

I

VCC/2
VCC/2

1.5 V

1.5 V

V

M

tr/t

f

≤2 ns

≤2 ns
≤2.5 ns
≤2.5 ns

INPUTS

SN74LVC112A

DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP

WITH CLEAR AND PRESET

SCAS289L – JANUARY 1993 – REVISED AUGUST 2005

PARAMETER MEASUREMENT INFORMATION

Figure 1. Load Circuit and Voltage Waveforms

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