Datasheet SN74LVC08AD, SN74LVC08ADBLE, SN74LVC08ADBR, SN74LVC08ADR, SN74LVC08APWLE Datasheet (Texas Instruments)

SN54LVC08A, SN74LVC08A

QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCAS283G – JANUARY 1993 – REVISED JUNE 1998

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

Typical V
< 0.8 V at V

D

Typical V
> 2 V at V

D

Inputs Accept Voltages to 5.5 V

D

Package Options Include Plastic

(Output Ground Bounce)

OLP

= 3.3 V, TA = 25°C

CC

(Output VOH Undershoot)

OHV

= 3.3 V, TA = 25°C

CC

Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK) and
Flat (W) Packages, and DIPs (J)

description

The SN54LVC08A quadruple 2-input positive­AND gate is designed for 2.7-V to 3.6-V V
operation and the SN74LVC08A quadruple
2-input positive-AND gate is designed for 1.65-V
to 3.6-V V

The ’LVC08A devices perform the Boolean
function

logic.

operation.

CC

Y+A • BorY+A

)

B

CC

in positive

SN54LVC08A...J OR W PACKAGE

SN74LVC08A. . . D, DB, OR PW PACKAGE

SN54LVC08A. . . FK PACKAGE

1Y

NC

2A

NC

2B

NC – No internal connection

(TOP VIEW)

1A

1

1B

2

1Y

3

2A

4

2B

5

2Y

6

GND

7

(TOP VIEW)

1B1ANC

3212019

4
5
6
7
8

910111213

2Y

GND

NC

14
13
12
11
10

9
8

CC

V

3Y

4B

18
17
16
15
14

3A

V
4B
4A
4Y
3B
3A
3Y

CC

4A
NC
4Y
NC
3B

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.

The SN54L VC08A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LVC08A is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each gate)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

INPUTS

A B

H H H

L XL

XLL

OUTPUT

Y

Copyright  1998, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN54LVC08A, SN74LVC08A
QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCAS283G – JANUARY 1993 – REVISED JUNE 1998

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, J, PW, and W packages.

†

1A
1B
2A
2B
3A
3B
4A
4B

1
2
4
5
9
10
12
13

&

3

1Y

6

2Y

8

3Y

11

4Y

logic diagram, each gate (positive logic)

A
B

Y

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ

Storage temperature range, T

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The value of VCC is provided in the recommended operating conditions table.

3. The package thermal impedance is calculated in accordance with JESD 51.

–0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 3): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DB package 158°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

‡

2

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UNIT

VCCSuppl

oltage

V

IOHHigh-level output current

mA

IOLLow-level output current

mA

SN54LVC08A, SN74LVC08A

QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCAS283G – JANUARY 1993 – REVISED JUNE 1998

recommended operating conditions (see Note 4)

SN54LVC08A SN74LVC08A

MIN MAX MIN MAX

pp

y v

V

V

V
V

∆t/∆v Input transition rise or fall rate 0 8 0 8 ns/V
T

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

High-level input voltage

IH

Low-level input voltage

IL

Input voltage 0 5.5 0 5.5 V

I

Output voltage 0 V

O

p

p

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

Operating 2 3.6 1.65 3.6
Data retention only 1.5 1.5
VCC = 1.65 V to 1.95 V 0.65 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 2 2
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 0.8 0.8

CC

VCC = 1.65 V –4
VCC = 2.3 V –8
VCC = 2.7 V –12 –12
VCC = 3 V –24 –24
VCC = 1.65 V 4
VCC = 2.3 V 8
VCC = 2.7 V 12 12
VCC = 3 V 24 24

, literature number SCBA004.

CC

1.7

0 V

0.7

CC

V

CC

V

V

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3

SN54LVC08A, SN74LVC08A

PARAMETER

TEST CONDITIONS

V

UNIT

I

100 µA

I

mA

I

100 µA

V

V

QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCAS283G – JANUARY 1993 – REVISED JUNE 1998

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54LVC08A SN74LVC08A

MIN TYP†MAX MIN TYP†MAX

V

= –

OH

IOH = –4 mA 1.65 V 1.2

V

OH

OL

I

I

I

CC

∆I

CC

C

†

i

All typical values are at VCC = 3.3 V, TA = 25°C.

IOH = –8 mA 2.3 V 1.7

= –12

OH

IOH = –24 mA 3 V 2.2 2.2

=

OL

IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.7
IOL = 12 mA 2.7 V 0.4 0.4
IOL = 24 mA 3 V 0.55 0.55
VI = 5.5 V or GND 3.6 V ±5 ±5 µA
VI = VCC or GND, IO = 0 3.6 V 10 10 µA
One input at VCC – 0.6 V,

Other inputs at VCC or GND
VI = VCC or GND 3.3 V 5 5 pF

CC

1.65 V to 3.6 V VCC–0.2

2.7 V to 3.6 V VCC–0.2

2.7 V 2.2 2.2
3 V 2.4 2.4

1.65 V to 3.6 V 0.2

2.7 V to 3.6 V 0.2

2.7 V to 3.6 V 500 500 µA

switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)

SN54LVC08A

PARAMETER

t

pd

FROM

(INPUT)

A or B

TO

(OUTPUT)

Y

VCC = 2.7 V

MIN MAX MIN MAX

VCC = 3.3 V

± 0.3 V

4.8 1 4.1 ns

UNIT

switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)

SN74LVC08A

PARAMETER

t

pd

‡

t

sk(o)

‡

Skew between any two outputs of the same package switching in the same direction

operating characteristics, T

C

Power dissipation capacitance per gate f = 10 MHz 7 9.8 10 pF

pd

FROM

(INPUT)

A or B

PARAMETER

A

(OUTPUT)

= 25°C

TO

Y

TEST CONDITIONS

VCC = 1.8 V

± 0.15 V

MIN MAX MIN MAX MIN MAX MIN MAX

1 9.8 1 6.9 4.8 1 4.1 ns

VCC = 2.5 V

± 0.2 V

VCC = 1.8 V

± 0.15 V

TYP TYP TYP

VCC = 2.7 V

VCC = 2.5 V

± 0.2 V

VCC = 3.3 V

± 0.3 V

VCC = 3.3 V

± 0.3 V

UNIT

1 ns

UNIT

4

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From Output

Under Test

CL = 30 pF

(see Note A)

SN54LVC08A, SN74LVC08A

QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCAS283G – JANUARY 1993 – REVISED JUNE 1998

PARAMETER MEASUREMENT INFORMATION

= 1.8 V ± 0.15 V

V

CC

2 × V

Open

GND

CC

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

1k Ω

1k Ω

S1

Open

2 × V

Open

CC

LOAD CIRCUIT

Timing

Input

t

Data

Input

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO = 50 Ω, tr≤2 ns, tf≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t

PLZ

F. t

PZL

G. t

PLH

VCC/2

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

and t

PHZ

and t

PZH

and t

PHL

VCC/2

t

su

are the same as t
are the same as ten.

are the same as tpd.

h

VCC/2

VCC/2 VCC/2

.

dis

t

PHL

V

0 V

V

0 V

V

0 V

V

V

CC

CC

CC

OH

OL

Input

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

VOLTAGE WAVEFORMS

PULSE DURATION

t

PZL

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

VCC/2

t

w

V

0 V

V

0 V

V

V

V

0 V

CC

CC

CC

OL

OH

VCC/2VCC/2

VCC/2VCC/2

t

PLZ

VOL + 0.15 V

t

PHZ

VOH – 0.15 V

Figure 1. Load Circuit and Voltage Waveforms

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5

SN54LVC08A, SN74LVC08A
QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCAS283G – JANUARY 1993 – REVISED JUNE 1998

PARAMETER MEASUREMENT INFORMATION

V

= 2.5 V ± 0.2 V

CC

2 × V

CC

Open

GND

From Output

Under Test

CL = 30 pF

(see Note A)

500 Ω

500 Ω

S1

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

Open

2 × V

GND

CC

LOAD CIRCUIT

Timing

Input

t

Data

Input

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO = 50 Ω, tr≤2 ns, tf≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t

PLZ

F. t

PZL

G. t

PLH

VCC/2

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

and t

PHZ

and t

PZH

and t

PHL

VCC/2

t

su

are the same as t
are the same as ten.
are the same as tpd.

h

VCC/2

VCC/2 VCC/2

.

dis

t

PHL

V

0 V

V

0 V

V

0 V

V

V

CC

CC

CC

OH

OL

Input

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOLTAGE WAVEFORMS

PULSE DURATION

t

PZL

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

VCC/2

t

w

V

0 V

V

0 V

V

V

V

0 V

CC

CC

CC

OL

OH

VCC/2VCC/2

VCC/2VCC/2

t

PLZ

VOL + 0.15 V

t

PHZ

VOH – 0.15 V

Figure 2. Load Circuit and Voltage Waveforms

6

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SN54LVC08A, SN74LVC08A

QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCAS283G – JANUARY 1993 – REVISED JUNE 1998

PARAMETER MEASUREMENT INFORMATION

= 2.7 V AND 3.3 V ± 0.3 V

V

CC

From Output

Under Test

CL = 50 pF

(see Note A)

Timing

Input

Data

Input

Input

t

PLH

Output

500 Ω

500 Ω

LOAD CIRCUIT

1.5 V

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V 1.5 V

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

t

h

S1

t

PHL

6 V

GND

2.7 V

2.7 V

V

V

Open

0 V

0 V

2.7 V

0 V

OH

OL

Input

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

t

PZL

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

t

w

t

1.5 V

t

PHZ

1.5 V

Open

6 V

GND

1.5 V1.5 V

PLZ

VOL + 0.3 V

VOH – 0.3 V

2.7 V

0 V

2.7 V

0 V

3 V

V

OL

V

OH

0 V

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO = 50 Ω, tr≤2.5 ns, tf≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t

F. t

G. t

PLZ
PZL
PLH

and t
and t

and t

are the same as t

PHZ

are the same as ten.

PZH

are the same as tpd.

PHL

dis

.

Figure 3. Load Circuit and Voltage Waveforms

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7

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