TEXAS INSTRUMENTS SN54LVC08A, SN74LVC08A Technical data

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1 2 3 4 5 6 7

14 13 12 11 10

9 8

1A 1B 1Y 2A 2B 2Y

GND

V

CC

4B 4A 4Y 3B 3A 3Y

SN54LVC08A . . . J OR W PACKAGE

SN74LVC08A . . . D, DB, NS, OR PW PACKAGE

(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

4 5 6 7 8

18 17 16 15 14

4A NC 4Y NC 3B

1Y

NC

2A

NC

2B

1B1ANC

3Y

3A

V

4B

2Y

GND

NC

SN54LVC08A . . . FK PACKAGE

(TOP VIEW)

CC

NC - No internal connection

SN74LVC08A . . . RGY PACKAGE

(TOP VIEW)

1 14

7 8

2 3 4 5 6

13 12 11 10

9

4B 4A 4Y 3B 3A

1B 1Y 2A 2B 2Y

1A

3Y

V

GND

CC

Y  A • B or Y  A  B

SN54LVC08A, SN74LVC08A

QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCAS283P – JANUARY 1993 – REVISED AUGUST 2005

FEATURES

• Operate From 1.65 V to 3.6 V • Latch-Up Performance Exceeds 250 mA Per

• Specified From –40 ° C to 85 ° C, –40 ° C to 125 ° C, and –55 ° C to 125 ° C • ESD Protection Exceeds JESD 22

• Inputs Accept Voltages to 5.5 V – 2000-V Human-Body Model (A114-A)

• Max tpdof 4.1 ns at 3.3 V – 200-V Machine Model (A115-A)

• Typical V

<0.8 V at V

• Typical V >2 V at V

(Output Ground Bounce) – 1000-V Charged-Device Model (C101)

OLP

CC

OHV

CC

= 3.3 V, T

(Output V

= 3.3 V, T

= 25 ° C brk

A

Undershoot)

OH

= 25 ° C

A

JESD 17

brk

DESCRIPTION/ORDERING INFORMATION

The SN54LVC08A quadruple 2-input positive-AND gate is designed for 2.7-V to 3.6-V V SN74LVC08A quadruple 2-input positive-AND gate is designed for 1.65-V to 3.6-V V

The 'LVC08A devices perform the Boolean function Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

operation, and the

CC

operation.

CC

in positive logic.

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

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A B

Y

SN54LVC08A, SN74LVC08A QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCAS283P – JANUARY 1993 – REVISED AUGUST 2005

ORDERING INFORMATION

T

A

–40 ° C to 85 ° C QFN – RGY Reel of 1000 SN74LVC08ARGYR LC08A

SOIC – D Reel of 2500 SN74LVC08ADR LVC08A

–40 ° C to 125 ° C

–55 ° C to 125 ° C CFP – W Tube of 150 SNJ54LVC08AW SNJ54LVC08AW

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

SOP – NS Reel of 2000 SN74LVC08ANSR LVC08A SSOP – DB Reel of 2000 SN74LVC08ADBR LC08A

TSSOP – PW Reel of 2000 SN74LVC08APWR LC08A

CDIP – J Tube of 25 SNJ54LVC08AJ SNJ54LVC08AJ

LCCC – FK Tube of 55 SNJ54LVC08AFK SNJ54LVC08AFK

PACKAGE

(1)

Tube of 50 SN74LVC08AD

Reel of 250 SN74LVC08ADT

Tube of 90 SN74LVC08APW

Reel of 250 SN74LVC08APWT

FUNCTION TABLE

(EACH GATE)

INPUTS

A B

H H H

L X L

X L L

ORDERABLE PART NUMBER TOP-SIDE MARKING

OUTPUT

Y

LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)

2

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SN54LVC08A, SN74LVC08A

QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCAS283P – JANUARY 1993 – REVISED AUGUST 2005

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

V V V I

IK

I

OK

I

O

θ

JA

T P

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The value of V (4) The package thermal impedance is calculated in accordance with JESD 51-7. (5) The package thermal impedance is calculated in accordance with JESD 51-5. (6) For the D package: above 70 ° C, the value of P (7) For the DB, NS, and PW packages: above 60 ° C, the value of P

Supply voltage range –0.5 6.5 V

CC

Input voltage range

I

Output voltage range

O

(2)

(2) (3)

Input clamp current VI< 0 –50 mA Output clamp current VO< 0 –50 mA Continuous output current ± 50 mA Continuous current through V

Package thermal impedance NS package

Storage temperature range –65 150 ° C

stg

Power dissipation

tot

(6) (7)

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

is provided in the recommended operating conditions table.

CC

(1)

MIN MAX UNIT

–0.5 6.5 V –0.5 V

or GND ± 100 mA

CC

D package DB package

PW package RGY package

(4)

(4) (4)

(4)

(5)

CC

TA= –40 ° C to 125 ° C 500 mW

derates linearly with 8 mW/K.

tot

derates linearly with 5.5 mW/K.

tot

+ 0.5 V

86 96 76 ° C/W

113

47

3

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SN54LVC08A, SN74LVC08A QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCAS283P – JANUARY 1993 – REVISED AUGUST 2005

Recommended Operating Conditions

V

V V V V

I

OH

I

OL

∆ t/ ∆ v Input transition rise or fall rate 8 ns/V

(1) All unused inputs of the device must be held at V

Supply voltage V

CC

High-level input voltage V

IH

Low-level input voltage V

IL

Input voltage 0 5.5 V

I

Output voltage 0 V

O

High-level output current mA

Low-level output current mA

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

(1)

Operating 2 3.6 Data retention only 1.5

= 2.7 V to 3.6 V 2 V

CC

= 2.7 V to 3.6 V 0.8 V

CC

V

= 2.7 V –12

CC

V

= 3 V –24

CC

V

= 2.7 V 12

CC

V

= 3 V 24

CC

or GND to ensure proper device operation. Refer to the TI application report,

CC

SN54LVC08A

–55 ° C to 125 ° C UNIT

MIN MAX

V

CC

Recommended Operating Conditions

(1)

SN74LVC08A TA= 25° C –40 ° C to 85 ° C –40 ° C to 125° C UNIT MIN MAX MIN MAX MIN MAX

V

Supply voltage V

CC

High-level

V

IH

input voltage

Low-level

V

IL

input voltage

V

Input voltage 0 5.5 0 5.5 0 5.5 V

I

V

Output voltage 0 V

O

High-level

I

OH

output current

Low-level

I

OL

output current

Operating 1.65 3.6 1.65 3.6 1.65 3.6 Data retention only 1.5 1.5 1.5 V

= 1.65 V to 1.95 V 0.65 × V

CC

V

= 2.3 V to 2.7 V 1.7 1.7 1.7 V

CC

V

= 2.7 V to 3.6 V 2 2 2

CC

V

= 1.65 V to 1.95 V 0.35 × V

CC

V

= 2.3 V to 2.7 V 0.7 0.7 0.7 V

CC

V

= 2.7 V to 3.6 V 0.8 0.8 0.8

CC

V

= 1.65 V –4 –4 –4

CC

V

= 2.3 V –8 –8 –8

CC

V

= 2.7 V –12 –12 –12

CC

V

= 3 V –24 –24 –24

CC

V

= 1.65 V 4 4 4

CC

V

= 2.3 V 8 8 8

CC

V

= 2.7 V 12 12 12

CC

V

= 3 V 24 24 24

CC

0.65 × V

CC

0.35 × V

0 V

0.65 × V

CC

0.35 × V

0 V

∆ t/ ∆ v Input transition rise or fall rate 8 8 8 ns/V

(1) All unused inputs of the device must be held at V

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

or GND to ensure proper device operation. Refer to the TI application report,

CC

V

CC

mA

4

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QUADRUPLE 2-INPUT POSITIVE-AND GATES

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS V

IOH= –100 µ A 2.7 V to 3.6 V V

V

OH

V

OL

I

CC

∆ I

CC

C

i

(1) TA= 25 ° C

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS V

V

OH

V

OL

I

CC

∆ I

CC

C

i

IOH= –12 mA V

IOH= –24 mA 3 V 2.2 IOL= 100 µ A 2.7 V to 3.6 V 0.2 IOL= 12 mA 2.7 V 0.4 V IOL= 24 mA 3 V 0.55 VI= 5.5 V or GND 3.6 V ± 5 µ A VI= V One input at V VI= V

or GND, IO= 0 3.6 V 10 µ A

CC

– 0.6 V, Other inputs at V

CC

or GND 3.3 V 5 pF

CC

or GND 2.7 V to 3.6 V 500 µ A

CC

TA= 25 ° C –40 ° C to 85 ° C –40 ° C to 125 ° C UNIT

MIN TYP MAX MIN MAX MIN MAX

IOH= –100 µ A 1.65 V to 3.6 V V

– 0.2 V

CC

IOH= –4 mA 1.65 V 1.29 1.2 1.05 IOH= –8 mA 2.3 V 1.9 1.7 1.55

IOH= –12 mA

2.7 V 2.2 2.2 2.05 3 V 2.4 2.4 2.25

IOH= –24 mA 3 V 2.3 2.2 2 IOL= 100 µ A 1.65 V to 3.6 V 0.1 0.2 0.3 IOL= 4 mA 1.65 V 0.24 0.45 0.6 IOL= 8 mA 2.3 V 0.3 0.7 0.75 V IOL= 12 mA 2.7 V 0.4 0.4 0.6 IOL= 24 mA 3 V 0.55 0.55 0.8 VI= 5.5 V or GND 3.6 V ± 1 ± 5 ± 20 µ A VI= V One input at V

Other inputs at V VI= V

or GND, IO= 0 3.6 V 1 10 40 µ A

CC

– 0.6 V,

CC

or GND

CC

or GND 3.3 V 5 pF

CC

2.7 V to 3.6 V 500 500 5000 µ A

SN54LVC08A, SN74LVC08A

SCAS283P – JANUARY 1993 – REVISED AUGUST 2005

SN54LVC08A

CC

2.7 V 2.2 3 V 2.4

SN74LVC08A

CC

–55 ° C to 125 ° C UNIT MIN TYP

– 0.2

CC

– 0.2 V

(1)

– 0.3

CC

MAX

V

5

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SN54LVC08A, SN74LVC08A QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCAS283P – JANUARY 1993 – REVISED AUGUST 2005

Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )

PARAMETER V

t

pd

Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )

PARAMETER V

t

pd

t

sk(o)

FROM TO

(INPUT) (OUTPUT)

A or B Y ns

FROM TO

(INPUT) (OUTPUT)

A or B Y ns

CC

1.8 V ± 0.15 V 1 5 9.3 1 9.8 1 11.3

2.5 V ± 0.2 V 1 2.9 6.4 1 6.9 1 9

2.7 V 1 3 4.6 1 4.8 1 6

3.3 V ± 0.3 V 1 2.6 3.9 1 4.1 1 5.5

3.3 V ± 0.3 V 1 1.5 ns

TA= 25 ° C –40 ° C to 85 ° C –40 ° C to 125 ° C UNIT

MIN TYP MAX MIN MAX MIN MAX

CC

2.7 V 4.8

3.3 V ± 0.3 V 1 4.1

SN74LVC08A

SN54LVC08A

–55 ° C to 125 ° C UNIT

MIN MAX

Operating Characteristics

TA= 25 ° C

C

pd

PARAMETER V

Power dissipation capacitance per gate f = 10 MHz 2.5 V 9.8 pF

TEST

CONDITIONS

1.8 V 7

3.3 V 10

TYP UNIT

CC

6

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V

M

t

h

t

su

From Output

Under Test

C

L

(see Note A)

LOAD CIRCUIT

S1

V

LOAD

Open

GND

R

L

R

L

Data Input

Timing Input

V

I

0 V

V

I

0 V

t

w

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

t

PLH

t

PHL

t

PHL

t

PLH

V

OH

V

OH

V

OL

V

OL

V

I

0 V

Input

Output Waveform 1 S1 at V

LOAD

(see Note B)

Output Waveform 2

S1 at GND

(see Note B)

V

OL

V

OH

t

PZL

t

PZH

t

PLZ

t

PHZ

V

LOAD

/2

0 V

VOL + V

∆

VOH - V

∆

≈0 V

V

I

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

V

LOAD

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. t

PLZ

and t

PHZ

are the same as t

dis

.

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

and t

PHL

are the same as tpd.

H. All parameters and waveforms are not applicable to all devices.

Output

Control

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

I

V

M

V

M

1.8 V ± 0.15 V

2.5 V ± 0.2 V

2.7 V

3.3 V ± 0.3 V

1 kΩ 500 Ω 500 Ω 500 Ω

V

CC

R

L

2 × V

CC

2 × V

CC

6 V 6 V

V

LOAD

C

L

30 pF 30 pF 50 pF 50 pF

0.15 V

0.3 V

V

∆

V

CC

V

CC

2.7 V

V

I

VCC/2 VCC/2

1.5 V

V

M

tr/t

f

≤2 ns

≤2 ns ≤2.5 ns ≤2.5 ns

INPUTS

SN54LVC08A, SN74LVC08A

QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCAS283P – JANUARY 1993 – REVISED AUGUST 2005

PARAMETER MEASUREMENT INFORMATION

Figure 1. Load Circuit and Voltage Waveforms

7

PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status

5962-9753401Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N/ A for Pkg Type 5962-9753401QCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type 5962-9753401QDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type

SN74LVC08AD ACTIVE SOIC D 14 50 Green (RoHS &

SN74LVC08ADBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI

SN74LVC08ADBR ACTIVE SSOP DB 14 2000 Green (RoHS &

SN74LVC08ADBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS &

SN74LVC08ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS &

SN74LVC08ADE4 ACTIVE SOIC D 14 50 Green (RoHS &

SN74LVC08ADG4 ACTIVE SOIC D 14 50 Green (RoHS &

SN74LVC08ADR ACTIVE SOIC D 14 2500 Green (RoHS &

SN74LVC08ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS &

SN74LVC08ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS &

SN74LVC08ADT ACTIVE SOIC D 14 250 Green (RoHS &

SN74LVC08ADTE4 ACTIVE SOIC D 14 250 Green (RoHS &

SN74LVC08ADTG4 ACTIVE SOIC D 14 250 Green (RoHS &

SN74LVC08ANSR ACTIVE SO NS 14 2000 Green (RoHS &

SN74LVC08ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS &

SN74LVC08ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS &

SN74LVC08APW ACTIVE TSSOP PW 14 90 Green (RoHS &

SN74LVC08APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS &

SN74LVC08APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &

SN74LVC08APWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI

SN74LVC08APWR ACTIVE TSSOP PW 14 2000 Green (RoHS &

SN74LVC08APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS &

SN74LVC08APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &

SN74LVC08APWT ACTIVE TSSOP PW 14 250 Green (RoHS &

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

no Sb/Br)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

20-Mar-2008

(3)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

(2)

SN74LVC08APWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS &

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

20-Mar-2008

(3)

no Sb/Br)

SN74LVC08APWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LVC08AQDRG4Q1 ACTIVE SOIC D 14 2500 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LVC08ARGYR ACTIVE QFN RGY 14 1000 Green (RoHS &

CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

SN74LVC08ARGYRG4 ACTIVE QFN RGY 14 1000 Green (RoHS &

CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

SNJ54LVC08AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N/ A for Pkg Type

SNJ54LVC08AJ ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

SNJ54LVC08AW ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL INFORMATION

11-Mar-2008

*All dimensions are nominal

Device Package

Type

SN74LVC08ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1

SN74LVC08ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

SN74LVC08ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

SN74LVC08APWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1

SN74LVC08ARGYR QFN RGY 14 1000 180.0 12.4 3.85 3.85 1.35 8.0 12.0 Q1

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN74LVC08ADBR SSOP DB 14 2000 346.0 346.0 33.0

SN74LVC08ADR SOIC D 14 2500 346.0 346.0 33.0 SN74LVC08ANSR SO NS 14 2000 346.0 346.0 33.0 SN74LVC08APWR TSSOP PW 14 2000 346.0 346.0 29.0

SN74LVC08ARGYR QFN RGY 14 1000 190.5 212.7 31.8

Pack Materials-Page 2

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,65

28

1

2,00 MAX

0,38 0,22

15

14

A

0,05 MIN

0,15

5,60 5,00

M

8,20 7,40

Seating Plane

0,10

0,25 0,09

0°–ā8°

Gage Plane

0,25

0,95 0,55

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

14

6,50

5,905,90

2016

7,50

6,90

24

8,50

28

10,50

9,907,90

30

10,50

9,90

38

12,90

12,30

4040065 /E 12/01

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

14

0,30 0,19

8

4,50 4,30

PINS **

7

Seating Plane

0,15 0,05

8

1

A

DIM

6,60 6,20

14

0,10

M

0,10

0,15 NOM

0°–8°

2016

Gage Plane

24

0,25

0,75 0,50

28

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A SQ

B SQ

19

20

22

23

24

25

21

12826 27

12

1314151618 17

0.020 (0,51)

0.010 (0,25)

MIN

0.342

(8,69)

0.442

0.640

0.739

0.938

1.141

A

0.358 (9,09)

0.458

(11,63)

0.660

(16,76)

0.761

(19,32)(18,78)

0.962

(24,43)

1.165

(29,59)

NO. OF

TERMINALS

**

11

10

9

8

7

6

5

432

20

28

44

52

68

84

0.020 (0,51)

0.010 (0,25)

(11,23)

(16,26)

(23,83)

(28,99)

MINMAX

0.307 (7,80)

0.406

(10,31)

0.495

(12,58)

0.495

(12,58)

0.850 (21,6)

1.047 (26,6)

0.080 (2,03)

0.064 (1,63)

B

MAX

0.358 (9,09)

0.458

(11,63)

0.560

(14,22)

0.560

(14,22)

0.858 (21,8)

1.063 (27,0)

0.055 (1,40)

0.045 (1,14)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated.

E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

4040140/D 10/96

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TEXAS INSTRUMENTS SN54LVC08A, SN74LVC08A Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

DESCRIPTION/ORDERING INFORMATION

Absolute Maximum Ratings

Recommended Operating Conditions

Recommended Operating Conditions

Electrical Characteristics

Electrical Characteristics

Switching Characteristics

Switching Characteristics

Operating Characteristics

PARAMETER MEASUREMENT INFORMATION