Texas Instruments SN74LVC07AD, SN74LVC07ADBR, SN74LVC07ADGVR, SN74LVC07ADR, SN74LVC07APWLE Datasheet
...
SN54LVC07A, SN74LVC07A
HEX BUFFERS/DRIVERS
WITH OPEN-DRAIN OUTPUTS
SCAS595H – OCTOBER 1997 – REVISED FEBRUARY 2000
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Inputs and Open-Drain Outputs Accept
Voltages Up to 5.5 V
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic
Small-Outline (D), Thin Very Small-Outline
(DGV), Thin Shrink Small-Outline (PW)
Packages, and Ceramic Flat (W) Packages,
Ceramic Chip Carriers (FK), and DIPs (J)
description
These hex buffers/drivers are designed for 1.65-V
to 5.5-V VCC operation.
The outputs of the ’LVC07A devices are open
drain and can be connected to other open-drain
outputs to implement active-low wired-OR or
active-high wired-AND functions. The maximum
sink current is 24 mA.
Inputs can be driven from 1.8-V, 2.5-V, 3.3-V
(LVTTL), or 5-V (CMOS) devices. This feature
allows the use of these devices as translators in
a mixed-system environment.
The SN54LVC07A is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74LVC07A is characterized for
operation from –40°C to 85°C.
SN54LVC07A...J OR W PACKAGE
SN74LVC07A. . . D, DGV, OR PW PACKAGE
SN54LVC07A. . . FK PACKAGE
2A
NC
2Y
NC
3A
NC – No internal connection
(TOP VIEW)
1A
1
1Y
2
2A
3
2Y
4
3A
5
3Y
6
GND
7
(TOP VIEW)
1Y1ANC
3212019
4
5
6
7
8
910111213
3Y
GND
NC
14
13
12
11
10
9
8
CC
V
4Y
V
6A
6Y
5A
5Y
4A
4Y
6A
18
17
16
15
14
4A
CC
6Y
NC
5A
NC
5Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
FUNCTION TABLE
(each buffer/driver)
INPUTAOUTPUT
Y
H H
L L
Copyright 2000, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54LVC07A, SN74LVC07A
HEX BUFFERS/DRIVERS
WITH OPEN-DRAIN OUTPUTS
SCAS595H – OCTOBER 1997 – REVISED FEBRUARY 2000
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DGV, J, PW, and W packages.
†
10
12
2
1Y
4
2Y
6
3Y
8
4Y
5Y
6Y
1A
2A
3A
4A
5A
6A
1
3
5
9
11
13
1
logic diagram, each buffer/driver (positive logic)
AY
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DGV package 182°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
‡
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
VIHHigh-level input voltage
V
VILLow-level input voltage
V
PARAMETER
TEST CONDITIONS
V
UNIT
V
I
mA
V
I
mA
SN54LVC07A, SN74LVC07A
HEX BUFFERS/DRIVERS
WITH OPEN-DRAIN OUTPUTS
SCAS595H – OCTOBER 1997 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 3)
SN54LVC07A SN74LVC07A
MIN MAX MIN MAX
V
V
V
I
OL
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 1.65 5.5 1.65 5.5 V
CC
VCC = 1.65 V to 1.95 V 0.65 × V
p
p
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 5.5 0 5.5 V
O
Low-level output current
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
VCC = 2.3 V to 2.7 V 1.7 1.7
VCC = 2.7 V to 3.6 V 2 2
VCC = 4.5 V to 5.5 V 0.7 × V
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V 0.7 0.7
VCC = 2.7 V to 3.6 V 0.8 0.8
VCC = 4.5 V to 5.5 V 0.3 × V
VCC = 1.65 V 4 4
VCC = 2.3 V 12 12
VCC = 2.7 V
VCC = 3 V 24 24
VCC = 4.5 V 24 24
, literature number SCBA004.
CC
CC
12 12
CC
CC
0.65 × V
0.7 × V
CC
CC
0.35 × V
0.3 × V
CC
CC
mA
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVC07A SN74LVC07A
MIN TYP†MAX MIN TYP†MAX
IOL = 100 µA 1.65 V to 5.5 V 0.2 0.2
IOL = 4 mA 1.65 V 0.45 0.45
OL
I
I
I
CC
∆I
CC
C
†
All typical values are at VCC = 3.3 V, TA = 25°C.
i
= 12
OL
= 24
OL
VI = 5.5 V or GND 3.6 V ±5 ±5 µA
VI = VCC or GND, IO = 0 3.6 V 10 10 µA
One input at VCC – 0.6 V,
Other inputs at VCC or GND
VI = VCC or GND 3.3 V 5 5 pF
CC
2.3 V 0.7 0.7
2.7 V 0.4 0.4
3 V 0.55 0.55
4.5 V
2.7 V to 3.6 V 500 500 µA
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54LVC07A, SN74LVC07A
CONDITIONS
HEX BUFFERS/DRIVERS
WITH OPEN-DRAIN OUTPUTS
SCAS595H – OCTOBER 1997 – REVISED FEBRUARY 2000
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 4)
SN54LVC07A
PARAMETER
t
pd
FROM
(INPUT)TO(OUTPUT)
A Y 1 3.5 1 2.8 3 1 2.9 1 2.6 ns
switching characteristics over recommended operating free-air temperature range, (unless
otherwise noted) (see Figures 1 through 4)
PARAMETER
t
pd
FROM
(INPUT)TO(OUTPUT)
A Y 1 3.5 1 2.8 3 1 2.9 1 2.6 ns
VCC = 1.8 V
± 0.15 V
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
VCC = 1.8 V
± 0.15 V
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
VCC = 2.5 V
± 0.2 V
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
SN74LVC07A
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
VCC = 5 V
± 0.5 V
UNIT
UNIT
operating characteristics, T
PARAMETER
C
Power dissipation capacitance
pd
per buffer/driver
= 25°C
A
TEST
f = 10 MHz 1.8 2 2.5 3.78 pF
VCC = 1.8 V
± 0.15 V
TYP TYP TYP TYP
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 30 pF
(see Note A)
SN54LVC07A, SN74LVC07A
WITH OPEN-DRAIN OUTPUTS
SCAS595H – OCTOBER 1997 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
= 1.8 V ± 0.15 V
V
CC
2 × V
Open
GND
CC
TEST S1
t
(see Note F)
PZL
t
(see Note G)
PLZ
t
PHZ/tPZH
1 kΩ
1 kΩ
S1
HEX BUFFERS/DRIVERS
2 × V
CC
2 × V
CC
2 × V
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. Since this device has open-drain outputs, t
F. t
PZL
G. t
PLZ
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
is measured at VCC/2.
is measured at VOL + 0.15 V.
VCC/2
t
su
h
VCC/2
VCC/2 VCC/2
t
PHL
PLZ
V
CC
0 V
V
CC
0 V
V
CC
0 V
V
CC
V
OL
and t
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at 2 × V
(see Note B)
are the same as tpd.
PZL
Input
CC
CC
t
w
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
VCC/2
t
PZH
VCC/2
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VCC – 0.15 V
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
CC
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54LVC07A, SN74LVC07A
HEX BUFFERS/DRIVERS
WITH OPEN-DRAIN OUTPUTS
SCAS595H – OCTOBER 1997 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 30 pF
(see Note A)
500 Ω
500 Ω
S1
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
GND
TEST S1
t
(see Note F)
PZL
t
(see Note G)
PLZ
t
PHZ/tPZH
2 × V
2 × V
2 × V
CC
CC
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. Since this device has open-drain outputs, t
F. t
PZL
G. t
PLZ
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
is measured at VCC/2.
is measured at VOL + 0.15 V.
VCC/2
t
su
h
VCC/2
VCC/2 VCC/2
t
PHL
PLZ
V
CC
0 V
V
CC
0 V
V
CC
0 V
V
CC
V
OL
and t
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at 2 × V
(see Note B)
are the same as tpd.
PZL
Input
CC
CC
t
w
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
VCC/2
t
PZH
VCC/2
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VCC – 0.15 V
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
CC
Figure 2. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 50 pF
(see Note A)
SN54LVC07A, SN74LVC07A
WITH OPEN-DRAIN OUTPUTS
SCAS595H – OCTOBER 1997 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
= 2.7 AND 3.3 V ± 0.3 V
V
CC
6 V
500 Ω
500 Ω
S1
Open
GND
TEST S1
t
(see Note F)
PZL
t
(see Note G)
PLZ
t
PHZ/tPZH
HEX BUFFERS/DRIVERS
6 V
6 V
6 V
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. Since this device has open-drain outputs, t
F. t
PZL
G. t
PLZ
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
is measured at 1.5 V.
is measured at VOL + 0.3 V.
1.5 V
t
su
h
1.5 V
t
PLH
1.5 V 1.5 V
t
PHL
PLZ
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
and t
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at 6 V
(see Note B)
are the same as tpd.
PZL
Input
t
w
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
1.5 V1.5 V
1.5 V1.5 V
t
PLZ
VOL + 0.3 V
t
PHZ
2.7 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
3 V
0 V
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN54LVC07A, SN74LVC07A
HEX BUFFERS/DRIVERS
WITH OPEN-DRAIN OUTPUTS
SCAS595H – OCTOBER 1997 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
500 Ω
S1
= 5 V ± 0.5 V
V
CC
2 × V
CC
Open
GND
TEST S1
t
(see Note F)
PZL
t
(see Note G)
PLZ
t
PHZ/tPZH
2 × V
2 × V
7 V
CC
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. Since this device has open-drain outputs, t
F. t
PZL
G. t
PLZ
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
is measured at VCC/2.
is measured at VOL + 0.3 V.
1.5 V
t
su
h
1.5 V
t
PLH
1.5 V 1.5 V
t
PHL
PLZ
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
and t
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at 7 V
(see Note B)
are the same as tpd.
PZL
Input
CC
t
w
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
VCC/2
t
PZH
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
1.5 V1.5 V
VCC/2VCC/2
t
VOL + 0.3 V
t
3.2 V
PLZ
PHZ
3 V
0 V
V
CC
0 V
V
CC
V
OL
3.5 V
0 V
Figure 4. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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performed, except those mandated by government requirements.
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Copyright 2000, Texas Instruments Incorporated
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