Texas Instruments SN74LVC06APWLE, SN74LVC06APWR, SN74LVC06AD, SN74LVC06ADBR, SN74LVC06ADGVR Datasheet
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SN54LVC06A, SN74LVC06A
HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-DRAIN OUTPUTS
SCAS596E – OCTOBER 1997 – REVISED SEPTEMBER 1999
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Inputs and Open-Drain Outputs Accept
Voltages up to 5.5 V
D
Power Off Disables Outputs, Permitting
Live Insertion
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic
Small-Outline (D), Thin Very Small-Outline
(DGV), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and DIPs (J)
description
These hex inverter buffers/drivers are designed
for 1.65-V to 3.6-V VCC operation.
The outputs of the ’LVC06A devices are open
drain and can be connected to other open-drain
outputs to implement active-low wired-OR or
active-high wired-AND functions. The maximum
sink current is 24 mA.
Inputs can be driven from either 3.3-V or 5-V
devices. This feature allows the use of these
devices as translators in a mixed 3.3-V/5-V
system environment.
SN54LVC06A...J OR W PACKAGE
SN74LVC06A. . . D, DGV, OR PW PACKAGE
SN54LVC06A. . . FK PACKAGE
2A
NC
2Y
NC
3A
NC – No internal connection
(TOP VIEW)
1A
1
1Y
2
2A
3
2Y
4
3A
5
3Y
6
GND
7
(TOP VIEW)
1Y1ANC
3212019
4
5
6
7
8
910111213
3Y
GND
14
13
12
11
10
NC
V
CC
6A
6Y
5A
5Y
4A
9
4Y
8
CC
6A
V
6Y
18
NC
17
5A
16
NC
15
5Y
14
4Y
4A
The SN54LVC06A is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74LVC06A is characterized for
operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
FUNCTION TABLE
(each inverter)
INPUT
OUTPUT
A
H L
L H
Y
Copyright 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54LVC06A, SN74LVC06A
HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-DRAIN OUTPUTS
SCAS596E – OCTOBER 1997 – REVISED SEPTEMBER 1999
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DGV, and PW packages.
†
10
12
2
1Y
4
2Y
6
3Y
8
4Y
5Y
6Y
1A
2A
3A
4A
5A
6A
1
3
5
9
11
13
1
logic diagram, each inverter (positive logic)
AY
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
Output voltage range, VO –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
Package thermal impedance, θJA (see Note 2): D package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
DGV package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
‡
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
VCCSuppl
oltage
V
IOLLow-level output current
mA
PARAMETER
TEST CONDITIONS
V
UNIT
SN54LVC06A, SN74LVC06A
HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-DRAIN OUTPUTS
SCAS596E – OCTOBER 1997 – REVISED SEPTEMBER 1999
recommended operating conditions (see Note 4)
SN54LVC06A SN74LVC06A
MIN MAX MIN MAX
pp
y v
V
V
V
V
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 5.5 0 5.5 V
O
p
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
Operating 1.65 5.5 1.65 5.5
Data retention only 1.5 1.5
VCC = 1.65 V to 1.95 V 0.65 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 2 2
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 0.8 0.8
VCC = 1.65 V 4 4
VCC = 2.3 V 8 8
VCC = 2.7 V 12 12
VCC = 3 V 24 24
, literature number SCBA004.
CC
1.7 1.7
0.7 0.7
CC
0.65 × V
CC
0.35 × V
V
CC
V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVC06A SN74LVC06A
MIN TYP†MAX MIN TYP†MAX
V
IOL = 100 µA 1.65 V to 3.6 V 0.2 0.2
IOL = 4 mA 1.65 V 0.45 0.45
V
OL
I
I
I
off
I
CC
∆I
CC
C
†
All typical values are at VCC = 3.3 V, TA = 25°C.
i
IOL = 8 mA 2.3 V 0.7 0.7
IOL = 12 mA 2.7 V 0.4 0.4
IOL = 24 mA 3 V 0.55 0.55
VI = 5.5 V or GND 3.6 V ±5 ±5 µA
VI or VO = 5.5 V 0 ±10 µA
VI = VCC or GND, IO = 0 3.6 V 10 10 µA
One input at VCC – 0.6 V,
Other inputs at VCC or GND
VI = VCC or GND 3.3 V 5 5 pF
CC
2.7 V to 3.6 V 500 500 µA
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
SN54LVC06A
PARAMETER
t
pd
FROM
(INPUT)
A Y 1.4 3.9 1 3.1 3.9 1 3.7 ns
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
MIN MAX MIN MAX MIN MAX MIN MAX
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54LVC06A, SN74LVC06A
CONDITIONS
HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-DRAIN OUTPUTS
SCAS596E – OCTOBER 1997 – REVISED SEPTEMBER 1999
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
SN74LVC06A
PARAMETER
t
pd
FROM
(INPUT)
A Y 1.4 3.9 1 3.1 3.9 1 3.7 ns
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
MIN MAX MIN MAX MIN MAX MIN MAX
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
operating characteristics, T
PARAMETER
C
Power dissipation capacitance per buffer/driver f = 10 MHz 2.1 2.3 2.5 pF
pd
= 25°C
A
TEST
VCC = 1.8 V
± 0.15 V
TYP TYP TYP
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
UNIT
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 30 pF
(see Note A)
SN54LVC06A, SN74LVC06A
HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-DRAIN OUTPUTS
SCAS596E – OCTOBER 1997 – REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
= 1.8 V ± 0.15 V
V
CC
2 × V
Open
GND
CC
TEST S1
t
(see Note F)
PZL
t
(see Note G)
PLZ
t
PHZ/tPZH
1 kΩ
1 kΩ
S1
2 × V
2 × V
2 × V
CC
CC
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. Since this device has open-drain outputs, t
F. t
PZL
G. t
PLZ
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
is measured at VCC/2.
is measured at VOL + 0.15 V.
VCC/2
t
su
h
VCC/2
VCC/2 VCC/2
t
PHL
PLZ
V
CC
0 V
V
CC
0 V
V
CC
0 V
V
CC
V
OL
and t
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at 2 × V
(see Note B)
are the same as tpd.
PZL
Input
CC
CC
t
w
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
VCC/2
t
PZH
VCC/2
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VCC – 0.15 V
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
CC
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54LVC06A, SN74LVC06A
HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-DRAIN OUTPUTS
SCAS596E – OCTOBER 1997 – REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 30 pF
(see Note A)
500 Ω
500 Ω
S1
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
GND
TEST S1
t
(see Note F)
PZL
t
(see Note G)
PLZ
t
PHZ/tPZH
2 × V
2 × V
2 × V
CC
CC
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. Since this device has open-drain outputs, t
F. t
PZL
G. t
PLZ
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
is measured at VCC/2.
is measured at VOL + 0.15 V.
VCC/2
t
su
h
VCC/2
VCC/2 VCC/2
t
PHL
PLZ
V
CC
0 V
V
CC
0 V
V
CC
0 V
V
CC
V
OL
and t
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at 2 × V
(see Note B)
are the same as tpd.
PZL
Input
CC
CC
t
w
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
VCC/2
t
PZH
VCC/2
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VCC – 0.15 V
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
CC
Figure 2. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 50 pF
(see Note A)
SN54LVC06A, SN74LVC06A
HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-DRAIN OUTPUTS
SCAS596E – OCTOBER 1997 – REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
= 2.7 AND 3.3 V ± 0.3 V
V
CC
6 V
500 Ω
500 Ω
S1
Open
GND
t
(see Note F)
PZL
t
(see Note G)
PLZ
t
PHZ/tPZH
TEST S1
6 V
6 V
6 V
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. Since this device has open-drain outputs, t
F. t
PZL
G. t
PLZ
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
is measured at 1.5 V.
is measured at VOL + 0.3 V.
1.5 V
t
su
h
1.5 V
t
PLH
1.5 V 1.5 V
t
PHL
PLZ
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
and t
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at 6 V
(see Note B)
are the same as tpd.
PZL
Input
t
w
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
1.5 V1.5 V
1.5 V1.5 V
t
PLZ
VOL + 0.3 V
t
PHZ
2.7 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
3 V
0 V
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 1999, Texas Instruments Incorporated
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