Datasheet SN74LVC02AD, SN74LVC02ADBLE, SN74LVC02ADBR, SN74LVC02ADR, SN74LVC02APWLE Datasheet (Texas Instruments)
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SN54LVC02A, SN74LVC02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCAS280I – JANUARY 1993 – REVISED OCTOBER 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
T ypical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, TA = 25°C
D
T ypical V
OHV
(Output VOH Undershoot)
> 2 V at V
CC
= 3.3 V, TA = 25°C
D
Inputs Accept Voltages to 5.5 V
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW)
Packages, Ceramic Flat (W), Chip Carriers
(FK), and DIPs (J)
description
The SN54LVC02A quadruple 2-input positiveNOR gate is designed for 2.7-V to 3.6-V V
CC
operation and the SN74LVC02A quadruple
2-input positive-NOR gate is designed for 1.65-V
to 3.6-V V
CC
operation.
The ’LVC02A devices perform the Boolean
function Y = A + B
or Y = A • B in positive logic.
Inputs can be driven from either 3.3-V or 5-V
devices. This feature allows the use of these
devices as translators in a mixed 3.3-V/5-V
system environment.
The SN54LVC02A is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74LVC02A is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
A B
Y
H X L
X HL
LLH
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1Y
1A
1B
2Y
2A
2B
GND
V
CC
4Y
4B
4A
3Y
3B
3A
SN54LVC02A...J OR W PACKAGE
SN74LVC02A. . . D, DB, OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4B
NC
4A
NC
3Y
1B
NC
2Y
NC
2A
1A1YNC
3A
3B
V
4Y
2B
GND
NC
SN54LVC02A. . . FK PACKAGE
(TOP VIEW)
CC
NC – No internal connection
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54LVC02A, SN74LVC02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCAS280I – JANUARY 1993 – REVISED OCTOBER 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
2
1A
3
1B
1Y
1
5
2A
6
2B
2Y
4
8
3A
9
3B
3Y
10
11
4A
12
4B
4Y
13
≥ 1
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, PW, and W packages.
logic diagram, each gate (positive logic)
A
B
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply-voltage range, V
CC
–0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input-voltage range, V
I
(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output-voltage range, V
O
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 3): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 158°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
SN54LVC02A, SN74LVC02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCAS280I – JANUARY 1993 – REVISED OCTOBER 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
SN54LVC02A SN74LVC02A
MIN MAX MIN MAX
UNIT
pp
Operating 2 3.6 1.65 3.6
VCCSuppl
y v
oltage
Data retention only 1.5 1.5
V
VCC = 1.65 V to 1.95 V 0.65 × V
CC
V
IH
High-level input voltage
VCC = 2.3 V to 2.7 V
1.7
V
VCC = 2.7 V to 3.6 V 2 2
VCC = 1.65 V to 1.95 V 0.35 × V
CC
V
IL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
V
VCC = 2.7 V to 3.6 V 0.8 0.8
V
I
Input voltage 0 5.5 0 5.5 V
V
O
Output voltage 0 V
CC
0 V
CC
V
VCC = 1.65 V –4
p
VCC = 2.3 V –8
IOHHigh-level output current
VCC = 2.7 V –12 –12
mA
VCC = 3 V –24 –24
VCC = 1.65 V 4
p
VCC = 2.3 V 8
IOLLow-level output current
VCC = 2.7 V 12 12
mA
VCC = 3 V 24 24
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
SN54LVC02A, SN74LVC02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCAS280I – JANUARY 1993 – REVISED OCTOBER 1998
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVC02A SN74LVC02A
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP†MAX MIN TYP†MAX
UNIT
1.65 V to 3.6 V VCC–0.2
I
OH
= –
100 µA
2.7 V to 3.6 V VCC–0.2
IOH = –4 mA 1.65 V 1.2
V
OH
IOH = –8 mA 2.3 V 1.7
V
2.7 V 2.2 2.2
I
OH
= –12
mA
3 V 2.4 2.4
IOH = –24 mA 3 V 2.2 2.2
1.65 V to 3.6 V 0.2
I
OL
=
100 µA
2.7 V to 3.6 V 0.2
IOL = 4 mA 1.65 V 0.45
V
OL
IOL = 8 mA 2.3 V 0.7
V
IOL = 12 mA 2.7 V 0.4 0.4
IOL = 24 mA 3 V 0.55 0.55
I
I
VI = 5.5 V or GND 3.6 V ±5 ±5 µA
I
CC
VI = VCC or GND, IO = 0 3.6 V 10 10 µA
∆I
CC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
2.7 V to 3.6 V 500 500 µA
C
i
VI = VCC or GND 3.3 V 5 5 pF
†
All typical values are at VCC = 3.3 V, TA = 25°C.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
SN54LVC02A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
MIN MAX MIN MAX
t
pd
A or B Y 5.4 1 4.4 ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
SN74LVC02A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
TYP MIN MAX MIN MAX MIN MAX
t
pd
A or B Y 13.4 1 7.4 5.4 1 4.4 ns
t
sk(o)
‡
1 ns
‡
Skew between any two outputs of the same package switching in the same direction
operating characteristics, T
A
= 25°C
TEST
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER
CONDITIONS
TYP TYP TYP
UNIT
C
pd
Power dissipation capacitance per gate f = 10 MHz 7.5 8.5 9.5 pF
SN54LVC02A, SN74LVC02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCAS280I – JANUARY 1993 – REVISED OCTOBER 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 1.8 V ± 0.15 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
1 kΩ
1 kΩ
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
V
CC
0 V
0 V
t
w
V
CC
V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
0 V
V
CC
VCC/2
t
PHL
VCC/2 VCC/2
V
CC
0 V
V
OH
V
OL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
t
PLH
2 × V
CC
V
CC
Figure 1. Load Circuit and Voltage Waveforms
SN54LVC02A, SN74LVC02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCAS280I – JANUARY 1993 – REVISED OCTOBER 1998
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.5 V ± 0.2 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
V
CC
0 V
0 V
t
w
V
CC
V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
0 V
V
CC
VCC/2
t
PHL
VCC/2 VCC/2
V
CC
0 V
V
OH
V
OL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
t
PLH
2 × V
CC
V
CC
Figure 2. Load Circuit and Voltage Waveforms
SN54LVC02A, SN74LVC02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCAS280I – JANUARY 1993 – REVISED OCTOBER 1998
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.7 V AND 3.3 V ± 0.3 V
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
6 V
Open
GND
500 Ω
500 Ω
t
PLH
t
PHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V1.5 V
1.5 V 1.5 V
2.7 V
0 V
1.5 V 1.5 V
V
OH
V
OL
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
0 V
1.5 V
2.7 V
0 V
1.5 V 1.5 V
0 V
2.7 V
0 V
1.5 V 1.5 V
t
w
Input
2.7 V
2.7 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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Copyright 1998, Texas Instruments Incorporated
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