TEXAS INSTRUMENTS SN54LVC02A, SN74LVC02A Technical data

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1
2
3
4
5
6
7

14
13
12
11
10

9
8

1Y
1A
1B
2Y
2A
2B

GND

V

CC

4Y
4B
4A
3Y
3B
3A

SN54LVC02A . . . J OR W PACKAGE

SN74LVC02A . . . D, DB, NS, OR PW PACKAGE

(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

4
5
6
7
8

18
17
16
15
14

4B
NC
4A
NC
3Y

1B

NC

2Y

NC

2A

1A1YNC

3A

3B

V

4Y

2B

GND

NC

SN54LVC02A . . . FK PACKAGE

(TOP VIEW)

CC

NC - No internal connection

SN74LVC02A . . . RGY PACKAGE

(TOP VIEW)

1 14

7 8

2
3
4
5
6

13
12
11
10

9

4Y
4B
4A
3Y
3B

1A
1B
2Y
2A
2B

1Y

3A

V

GND

CC

SN54LVC02A, SN74LVC02A

QUADRUPLE 2-INPUT POSITIVE-NOR GATES

SCAS280Q – JANUARY 1993 – REVISED JULY 2005

FEATURES

• Operate From 1.65 V to 3.6 V • Latch-Up Performance Exceeds 250 mA Per

• Specified From –40°C to 85°C,
–40°C to 125°C, and –55°C to 125°C • ESD Protection Exceeds JESD 22

• Inputs Accept Voltages to 5.5 V – 2000-V Human-Body Model (A114-A)

• Max tpdof 4.4 ns at 3.3 V – 200-V Machine Model (A115-A)

• Typical V

<0.8 V at V

• Typical V
>2 V at V

(Output Ground Bounce) – 1000-V Charged-Device Model (C101)xxxxx

OLP

CC

OHV

CC

= 3.3 V, T

(Output V

= 3.3 V, T

= 25°C xxxxx

A

Undershoot)

OH

= 25°C

A

JESD 17

xxxxx

DESCRIPTION/ORDERING INFORMATION

The SN54LVC02A quadruple 2-input positive-NOR gate is designed for 2.7-V to 3.6-V V
SN74LVC02A quadruple 2-input positive-NOR gate is designed for 1.65-V to 3.6-V V

The 'LVC02A devices perform the Boolean function Y = A + B or Y = A ⋅ B in positive logic.

T

A

–40°C to 85°C QFN – RGY Reel of 1000 SN74LVC02ARGYR LC02A

SOIC – D Reel of 2500 SN74LVC02ADR LVC02A

–40°C to 125°C

–55°C to 125°C CFP – W Tube of 150 SNJ54LVC02AW SNJ54LVC02AW

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SOP – NS Reel of 2000 SN74LVC02ANSR LVC02A
SSOP – DB Reel of 2000 SN74LVC02ADBR LC02A

TSSOP – PW Reel of 2000 SN74LVC02APWR LC02A

CDIP – J Tube of 25 SNJ54LVC02AJ SNJ54LVC02AJ

LCCC – FK Tube of 55 SNJ54LVC02AFK SNJ54LVC02AFK

ORDERING INFORMATION

PACKAGE

(1)

Tube of 50 SN74LVC02AD

Reel of 250 SN74LVC02ADT

Tube of 90 SN74LVC02APW

Reel of 250 SN74LVC02APWT

operation.

CC

ORDERABLE PART NUMBER TOP-SIDE MARKING

Copyright © 1993–2005, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

operation, and the

CC

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A
B

Y

SN54LVC02A, SN74LVC02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES

SCAS280Q – JANUARY 1993 – REVISED JULY 2005

DESCRIPTION/ORDERING INFORMATION (CONTINUED)

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.

FUNCTION TABLE

(EACH GATE)

INPUTS

A B

H X L
X H L
L L H

LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)

OUTPUT

Y

Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

V

CC

V

I

V

O

I

IK

I

OK

I

O

θ

JA

T

stg

P

tot

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of V
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) The package thermal impedance is calculated in accordance with JESD 51-5.
(6) For the D package: above 70°C, the value of P
(7) For the DB, NS, and PW packages: above 60°C, the value of P

Supply voltage range –0.5 6.5 V
Input voltage range
Output voltage range

(2)

(2) (3)

–0.5 6.5 V

–0.5 V
Input clamp current VI< 0 –50 mA
Output clamp current VO< 0 –50 mA
Continuous output current ±50 mA
Continuous current through V

Package thermal impedance NS package

or GND ±100 mA

CC

D package
DB package

PW package
RGY package

(4)

(4)
(4)

(4)

(5)

Storage temperature range –65 150 °C
Power dissipation TA= –40°C to 125°C

(6) (7)

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

is provided in the recommended operating conditions table.

CC

derates linearly with 8 mW/K.

tot

derates linearly with 5.5 mW/K.

tot

+ 0.5 V

CC

86
96
76 °C/W

113

47

500 mW

2

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Recommended Operating Conditions

V

V
V
V
V

I

OH

I

OL

(1) All unused inputs of the device must be held at V

Supply voltage V

CC

High-level input voltage V

IH

Low-level input voltage V

IL

Input voltage 0 5.5 V

I

Output voltage 0 V

O

High-level output current mA

Low-level output current mA

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

SN54LVC02A, SN74LVC02A

QUADRUPLE 2-INPUT POSITIVE-NOR GATES

SCAS280Q – JANUARY 1993 – REVISED JULY 2005

(1)

Operating 2 3.6
Data retention only 1.5

= 2.7 V to 3.6 V 2 V

CC

= 2.7 V to 3.6 V 0.8 V

CC

V

= 2.7 V –12

CC

V

= 3 V –24

CC

V

= 2.7 V 12

CC

V

= 3 V 24

CC

or GND to ensure proper device operation. Refer to the TI application report,

CC

SN54LVC02A

–55 ° C to 125°C UNIT

MIN MAX

V

CC

Recommended Operating Conditions

V

V

V

V
V

I

OH

I

OL

Supply voltage V

CC

High-level

IH

input voltage

Low-level

IL

input voltage

Input voltage 0 5.5 0 5.5 0 5.5 V

I

Output voltage 0 V

O

High-level
output current

Low-level
output current

(1) All unused inputs of the device must be held at V

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

Operating 1.65 3.6 1.65 3.6 1.65 3.6
Data retention only 1.5 1.5 1.5
V

= 1.65 V to 1.95 V 0.65 × V

CC

V

= 2.3 V to 2.7 V 1.7 1.7 1.7 V

CC

V

= 2.7 V to 3.6 V 2 2 2

CC

V

= 1.65 V to 1.95 V 0.35 × V

CC

V

= 2.3 V to 2.7 V 0.7 0.7 0.7 V

CC

V

= 2.7 V to 3.6 V 0.8 0.8 0.8

CC

V

= 1.65 V –4 –4 –4

CC

V

= 2.3 V –8 –8 –8

CC

V

= 2.7 V –12 –12 –12

CC

V

= 3 V –24 –24 –24

CC

V

= 1.65 V 4 4 4

CC

V

= 2.3 V 8 8 8

CC

V

= 2.7 V 12 12 12

CC

V

= 3 V 24 24 24

CC

(1)

SN74LVC02A

TA= 25° C –40 ° C to 85° C –40 ° C to 125° C UNIT

MIN MAX MIN MAX MIN MAX

CC

or GND to ensure proper device operation. Refer to the TI application report,

CC

0.65 × V

CC

CC

CC

0.35 × V

0 V

0.65 × V

CC

CC

CC

0.35 × V

0 V

CC

V

CC

mA

mA

3

www.ti.com

SN54LVC02A, SN74LVC02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES

SCAS280Q – JANUARY 1993 – REVISED JULY 2005

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS V

IOH= –100 µ A 2.7 V to 3.6 V V

V

OH

V

OL

I

I

I

CC

∆ I

CC

C

i

(1) TA= 25°C

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PAR-

AMETER

V

OH

V

OL

I

I

I

CC

∆ I

CC

C

i

IOH= –12 mA V

IOH= –24 mA 3 V 2.2
IOL= 100 µ A 2.7 V to 3.6 V 0.2
IOL= 12 mA 2.7 V 0.4 V
IOL= 24 mA 3 V 0.55
VI= 5.5 V or GND 3.6 V ±5 µ A
VI= V
One input at V
VI= V

or GND, IO= 0 3.6 V 10 µ A

CC

– 0.6 V, Other inputs at V

CC

or GND 3.3 V 5

CC

TEST CONDITIONS V

CC

or GND 2.7 V to 3.6 V 500 µ A

CC

TA= 25°C –40 ° C to 85°C –40 ° C to 125°C UNIT

MIN TYP MAX MIN MAX MIN MAX

IOH= –100 µ A 1.65 V to 3.6 V V

– 0.2 V

CC

IOH= –4 mA 1.65 V 1.29 1.2 1.05
IOH= –8 mA 2.3 V 1.9 1.7 1.55

IOH= –12 mA

2.7 V 2.2 2.2 2.05
3 V 2.4 2.4 2.25

IOH= –24 mA 3 V 2.3 2.2 2
IOL= 100 µ A 1.65 V to 3.6 V 0.1 0.2 0.3
IOL= 4 mA 1.65 V 0.24 0.45 0.6
IOL= 8 mA 2.3 V 0.3 0.7 0.75 V
IOL= 12 mA 2.7 V 0.4 0.4 0.6
IOL= 24 mA 3 V 0.55 0.55 0.8
VI= 5.5 V or GND 3.6 V ±1 ±5 ±20 µ A
VI= V
One input at V

Other inputs at V
GND

VI= V

or GND, IO= 0 3.6 V 1 10 40 µ A

CC

– 0.6 V,

CC

or 2.7 V to 3.6 V 500 500 5000 µ A

CC

or GND 3.3 V 5 pF

CC

CC

2.7 V 2.2
3 V 2.4

SN74LVC02A

– 0.2 V

CC

SN54LVC02A

–55 ° C to 125°C UNIT

MIN TYP MAX

– 0.2

CC

(1)

– 0.3

CC

pF

V

4

www.ti.com

SN54LVC02A, SN74LVC02A

QUADRUPLE 2-INPUT POSITIVE-NOR GATES

SCAS280Q – JANUARY 1993 – REVISED JULY 2005

Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )

PARAMETER V

t

pd

Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )

PARAMETER V

t

pd

t

sk(o)

FROM TO

(INPUT) (OUTPUT)

A or B Y ns

FROM TO

(INPUT) (OUTPUT)

A or B Y ns

SN74LVC02A

CC

1.8 V ± 0.15 V 1 3.8 8.4 1 8.9 1 10.4

2.5 V ± 0.2 V 1 2.9 6.9 1 7.4 1 9.5

2.7 V 1 3 5.2 1 5.4 1 7

3.3 V ± 0.3 V 1 3.6 4.2 1 4.4 1 5.5

3.3 V ± 0.3 V 1 1.5 ns

TA= 25°C –40 ° C to 85°C –40 ° C to 125°C UNIT

MIN TYP MAX MIN MAX MIN MAX

CC

2.7 V 5.4

3.3 V ± 0.3 V 1 4.4

SN54LVC02A

–55 ° C to 125°C UNIT

MIN MAX

Operating Characteristics

TA= 25°C

C

pd

PARAMETER V

Power dissipation capacitance per gate f = 10 MHz 2.5 V 8.5 pF

TEST

CONDITIONS

CC

1.8 V 7.5

3.3 V 9.5

TYP UNIT

5

www.ti.com

V

M

t

h

t

su

From Output

Under Test

C

L

(see Note A)

LOAD CIRCUIT

S1

V

LOAD

Open

GND

R

L

R

L

Data Input

Timing Input

V

I

0 V

V

I

0 V

0 V

t

w

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

t

PLH

t

PHL

t

PHL

t

PLH

V

OH

V

OH

V

OL

V

OL

V

I

0 V

Input

Output
Waveform 1
S1 at V

LOAD

(see Note B)

Output
Waveform 2

S1 at GND

(see Note B)

V

OL

V

OH

t

PZL

t

PZH

t

PLZ

t

PHZ

V

LOAD

/2

0 V

VOL + V

∆

VOH - V

∆

≈0 V

V

I

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

V

LOAD

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. t

PLZ

and t

PHZ

are the same as t

dis

.

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

and t

PHL

are the same as tpd.

H. All parameters and waveforms are not applicable to all devices.

Output

Control

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

I

V

M

V

M

1.8 V ± 0.15 V

2.5 V ± 0.2 V

2.7 V

3.3 V ± 0.3 V

1 kΩ
500 Ω
500 Ω
500 Ω

V

CC

R

L

2 × V

CC

2 × V

CC

6 V
6 V

V

LOAD

C

L

30 pF
30 pF
50 pF
50 pF

0.15 V

0.15 V

0.3 V

0.3 V

V

∆

V

CC

V

CC

2.7 V

2.7 V

V

I

VCC/2
VCC/2

1.5 V

1.5 V

V

M

tr/t

f

≤2 ns

≤2 ns
≤2.5 ns
≤2.5 ns

INPUTS

SN54LVC02A, SN74LVC02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES

SCAS280Q – JANUARY 1993 – REVISED JULY 2005

PARAMETER MEASUREMENT INFORMATION

6

Figure 1. Load Circuit and Voltage Waveforms

PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status

5962-9760401Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-9760401QCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
5962-9760401QDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type

SN74LVC02AD ACTIVE SOIC D 14 50 Green (RoHS &

SN74LVC02ADBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI

SN74LVC02ADBR ACTIVE SSOP DB 14 2000 Green (RoHS &

SN74LVC02ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS &

SN74LVC02ADE4 ACTIVE SOIC D 14 50 Green (RoHS &

SN74LVC02ADG4 ACTIVE SOIC D 14 50 Green (RoHS &

SN74LVC02ADR ACTIVE SOIC D 14 2500 Green (RoHS &

SN74LVC02ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS &

SN74LVC02ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS &

SN74LVC02ADT ACTIVE SOIC D 14 250 Green (RoHS &

SN74LVC02ADTE4 ACTIVE SOIC D 14 250 Green (RoHS &

SN74LVC02ADTG4 ACTIVE SOIC D 14 250 Green (RoHS &

SN74LVC02ANSR ACTIVE SO NS 14 2000 Green (RoHS &

SN74LVC02ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS &

SN74LVC02ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS &

SN74LVC02APW ACTIVE TSSOP PW 14 90 Green (RoHS &

SN74LVC02APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS &

SN74LVC02APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &

SN74LVC02APWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI

SN74LVC02APWR ACTIVE TSSOP PW 14 2000 Green (RoHS &

SN74LVC02APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS &

SN74LVC02APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &

SN74LVC02APWT ACTIVE TSSOP PW 14 250 Green (RoHS &

SN74LVC02APWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS &

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

20-Mar-2008

(3)

Addendum-Page 1