Texas Instruments SN74LV74DR, SN74LV74PWLE, SN74LV74PWR, SN74LV74D, SN74LV74DBLE Datasheet

SN54LV74, SN74LV74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

EPIC

 (Enhanced-Performance Implanted

CMOS) 2-µ Process

D

T ypical V

OLP

(Output Ground Bounce)

< 0.8 V at V

CC

, TA = 25°C

D

T ypical V

OHV

(Output VOH Undershoot)

> 2 V at VCC, TA = 25°C

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17

D

Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs

description

These dual positive-edge-triggered D-type flip­flops are designed for 2.7-V to 5.5-V V

CC

operation.
A low level at the preset (PRE) or clear (CLR)

inputs sets or resets the outputs regardless of the
levels of the other inputs. When PRE and CLR are
inactive (high), data at the data (D) inputs meeting
the setup-time requirements is transferred to the
outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed
without affecting the levels at the outputs.

The SN74LV74 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.

The SN54L V74 is characterized for operation over the full military temperature range of –55 °C to 125°C. The
SN74LV74 is characterized for operation from –40°C to 85°C.

Copyright  1996, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

1
2
3
4
5
6
7

14
13
12
11
10

9
8

1CLR

1D
1CLK
1PRE

1Q

1Q

GND

V

CC

2CLR
2D
2CLK
2PRE
2Q
2Q

SN54LV74...J OR W PACKAGE

SN74LV74. . . D, DP, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

4
5
6
7
8

18
17
16
15
14

2D
NC
2CLK
NC
2PRE

1CLK

NC

1PRE

NC

1Q

1D

1CLR

NC

2Q

2Q

V

2CLR

1Q

GND

NC

SN54LV74. . . FK PACKAGE

(TOP VIEW)

CC

NC – No internal connection

EPIC is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54LV74, SN74LV74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

INPUTS

OUTPUTS

PRE CLR CLK D Q Q

L H X X H L
H LXXLH
L LXXH†H

†

H H ↑ HHL
H H ↑ LLH
H H L X Q

0

Q

0

†

This configuration is nonstable; that is, it does not
persist when PRE

or CLR returns to its inactive

(high) level.

logic symbol

†

S

4
3

1CLK

1D

2

1D

R

1

1Q

5

6

C1

10
11

2CLK

12

2D

13

2Q

9

8

1PRE

2PRE

1CLR

2CLR

1Q

2Q

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for D, DB, J, PW, and W packages.

logic diagram, each flip-flop (positive logic)

TG

C

C

TG

C

C

TG

C

C

C

C

TG

C

C

PRE

CLK

D

CLR

Q

Q

SN54LV74, SN74LV74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

O

(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum power dissipation at TA = 55°C (in still air) (see Note 3):D package 1.25 W. . . . . . . . . . . . . . . . . . .

DB or PW package 0.5 W. . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 7 V maximum.

3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.

recommended operating conditions (see Note 4)

SN54LV74 SN74LV74

UNIT

MIN MAX MIN MAX

UNIT

V

CC

Supply voltage 2.7 5.5 2.7 5.5 V

p

VCC = 2.7 V to 3.6 V 2 2

VIHHigh-level input voltage

VCC = 4.5 V to 5.5 V 3.15 3.15

V

p

VCC = 2.7 V to 3.6 V 0.8 0.8

VILLow-level input voltage

VCC = 4.5 V to 5.5 V 1.65 1.65

V

V

I

Input voltage 0 V

CC

0 V

CC

V

V

O

Output voltage 0 V

CC

0 V

CC

V

p

VCC = 2.7 V to 3.6 V –6 –6

IOHHigh-level output current

VCC = 4.5 V to 5.5 V –12 –12

mA

p

VCC = 2.7 V to 3.6 V 6 6

IOLLow-level output current

VCC = 4.5 V to 5.5 V 12 12

mA

∆t/∆v Input transition rise or fall rate 0 100 0 100 ns/V
T

A

Operating free-air temperature –55 125 –40 85 °C

NOTE 4: Unused inputs must be held high or low to prevent them from floating.

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design phase of development. Characteristic data and other
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change or discontinue these products without notice.