Texas Instruments SN74LV74AD, SN74LV74ADBLE, SN74LV74ADBR, SN74LV74ADGVR, SN74LV74ADR Datasheet

SN54LV74A, SN74LV74A

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

SCLS381D – AUGUST 1997 – REVISED JUNE 1998

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Process

D

T ypical V

OLP

(Output Ground Bounce)

< 0.8 V at V

CC

, TA = 25°C

D

T ypical V

OHV

(Output VOH Undershoot)

> 2 V at V

CC

, TA = 25°C

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)

description

These dual positive-edge-triggered D-type
flip-flops are designed for 2-V to 5.5-V V

CC

operation.
A low level at the preset (PRE

) or clear (CLR)
inputs sets or resets the outputs, regardless of the
levels of the other inputs. When PRE

and CLR are
inactive (high), data at the data (D) inputs meeting
the setup-time requirements is transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold-time interval, data
at the D input can be changed without affecting the
levels at the outputs.

The SN54LV74A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LV74A is characterized for operation from –40°C to 85°C.

Copyright  1998, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

1
2
3
4
5
6
7

14
13
12
11
10

9
8

1CLR

1D
1CLK
1PRE

1Q

1Q

GND

V

CC

2CLR
2D
2CLK
2PRE
2Q
2Q

SN54LV74A...J OR W PACKAGE

SN74LV74A. . . D, DB, DGV, NS, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

4
5
6
7
8

18
17
16
15
14

2D
NC
2CLK
NC
2PRE

1CLK

NC

1PRE

NC

1Q

1D

1CLR

NC

2Q

2Q

V

2CLR

1Q

GND

NC

SN54LV74A. . . FK PACKAGE

(TOP VIEW)

CC

NC – No internal connection

EPIC is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

SCLS381D – AUGUST 1997 – REVISED JUNE 1998

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

INPUTS

OUTPUTS

PRE CLR CLK D Q Q

L H X X H L
H LXXLH
LLXXH

†

H

†

HH↑HHL
HH↑LLH
HHLXQ

0

Q

0

†

This configuration is unstable; that is, it does not
persist when PRE

or CLR returns to its inactive

(high) level.

logic symbol

‡

S

4
3

1CLK

1D

2

1D

R

1

1Q

5

6

C1

10
11

2CLK

12

2D

13

2Q

9

8

1PRE

2PRE

1CLR

2CLR

1Q

2Q

‡

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.

logic diagram, each flip-flop (positive logic)

TG

C

C

TG

C

TG

C

C

C

C

TG

C

C

PRE

CLK

D

CLR

Q

Q

C

SN54LV74A, SN74LV74A

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

SCLS381D – AUGUST 1997 – REVISED JUNE 1998

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

O

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

OK

(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

O

(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through V

CC

or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 3): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DB package 158°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 182°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 7 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 4)

SN54LV74A SN74LV74A

MIN MAX MIN MAX

UNIT

V

CC

Supply voltage 2 5.5 2 5.5 V

VCC = 2 V 1.5 1.5

p

VCC = 2.3 V to 2.7 V VCC× 0.7 VCC× 0.7

VIHHigh-level input voltage

VCC = 3 V to 3.6 V VCC× 0.7 VCC× 0.7

V

VCC = 4.5 V to 5.5 V VCC× 0.7 VCC× 0.7
VCC = 2 V 0.5 0.5

p

VCC = 2.3 V to 2.7 V VCC× 0.3 VCC× 0.3

VILLow-level input voltage

VCC = 3 V to 3.6 V VCC× 0.3 VCC× 0.3

V

VCC = 4.5 V to 5.5 V VCC× 0.3 VCC× 0.3

V

I

Input voltage 0 5.5 0 5.5 V

V

O

Output voltage 0 V

CC

0 V

CC

V

VCC = 2 V –50 –50 µA

p

VCC = 2.3 V to 2.7 V –2 –2

IOHHigh-level output current

VCC = 3 V to 3.6 V –6 –6

mA
VCC = 4.5 V to 5.5 V –12 –12
VCC = 2 V 50 50 µA

p

VCC = 2.3 V to 2.7 V 2 2

IOLLow-level output current

VCC = 3 V to 3.6 V 6 6

mA
VCC = 4.5 V to 5.5 V 12 12
VCC = 2.3 V to 2.7 V 0 200 0 200

∆t/∆v Input transition rise or fall rate

VCC = 3 V to 3.6 V

0 100 0 100

ns/V

VCC = 4.5 V to 5.5 V 0 20 0 20

T

A

Operating free-air temperature –55 125 –40 85 °C

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

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design phase of development. Characteristic data and other
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change or discontinue these products without notice.