SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414D – APRIL 1998 – REVISED JANUARY 2000
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Typical V
(Output Ground Bounce)
OLP
<0.8 V at VCC = 3.3 V, TA = 25°C
D
T ypical V
at V
D
8-Bit Serial-In, Parallel-Out Shift
D
Shift Register Has Direct Clear
D
Latch-Up Performance Exceeds 250 mA Per
= 3.3 V, TA = 25°C
CC
(Output VOH Undershoot) >2 V
OHV
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Flat (W) Packages, Chip
Carriers (FK), and DIPs (J)
description
The ’LV595A devices are 8-bit shift registers
designed for 2-V to 5.5-V VCC operation.
These devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. The storage register has parallel
3-state outputs. Separate clocks are provided for
both the shift and storage register. The shift
register has a direct overriding clear (SRCLR
input, serial (SER) input, and a serial output for
cascading. When the output-enable (OE) input is
high, all outputs except QH′ are in the
high-impedance state.
SN54LV595A...J OR W PACKAGE
SN74LV595A. . . D, DB, NS, OR PW PACKAGE
SN54LV595A. . . FK PACKAGE
Q
D
Q
E
NC
Q
F
Q
G
NC – No internal connection
(TOP VIEW)
Q
1
B
Q
2
C
Q
3
D
Q
4
E
5
Q
F
6
Q
G
7
Q
H
GND
8
(TOP VIEW)
CQB
Q
3212019
4
5
6
7
8
910111213
H
Q
NC
GND
16
15
14
13
12
11
10
NC
9
VCCQ
′
H
Q
V
CC
Q
A
SER
OE
RCLK
SRCLK
SRCLR
Q
H′
A
SER
18
OE
17
NC
16
RCLK
15
14
SRCLK
SRCLR
)
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both
clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54L V595A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV595A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
SN54LV595A, SN74LV595A
FUNCTION
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414D – APRIL 1998 – REVISED JANUARY 2000
INPUTS
SER SRCLK SRCLR RCLK OE
X X X X H Outputs QA–QH are disabled.
X X X X L Outputs QA–QH are enabled.
X X L X X Shift register is cleared.
L ↑ H X X
H ↑ H X X
X ↓ H X X Shift-register state is not changed.
X XX↑ X Shift-register data is stored into the storage register.
X X X ↓ X Storage-register state is not changed.
FUNCTION TABLE
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, NS, PW, and W packages.
†
OE
RCLK
SRCLR
SRCLK
SER
13
12
10
11
14
EN3
R
1D
C2
SRG8
C1/
2D
2D
15
3
3
Q
A
1
Q
B
2
Q
C
3
Q
D
4
Q
E
5
Q
F
6
Q
G
7
Q
H
9
Q
H′
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
13
OE
SER
12
10
11
14
RCLK
SRCLR
SRCLK
1D
R
C1
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414D – APRIL 1998 – REVISED JANUARY 2000
Q
3D
C3
Q
15
Q
A
2D
R
2D
R
2D
R
2D
R
2D
R
2D
R
C2
C2
C2
C2
C2
C2
Q
Q
Q
Q
Q
Q
3D
3D
3D
3D
3D
3D
C3
C3
C3
C3
C3
C3
Q
Q
Q
Q
Q
Q
1
Q
B
2
Q
C
3
Q
D
4
Q
E
5
Q
F
6
Q
G
2D
C2
R
Pin numbers shown are for the D, DB, J, NS, PW, and W packages.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Q
3D
C3
7
Q
Q
H
9
Q
H′
3
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414D – APRIL 1998 – REVISED JANUARY 2000
timing diagram
SRCLK
SER
RCLK
SRCLR
OE
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
Q
H’
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414D – APRIL 1998 – REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range applied in the high or low state, V
Output voltage range applied in high-impedance or power-off state, VO (see Note 1) –0.5 V to 7 V. . . . . . .
Input clamp current, IIK (VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
Package thermal impedance, θJA (see Note 3): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . .
O
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54LV595A, SN74LV595A
UNIT
VIHHigh-level input voltage
V
VILLow-level input voltage
V
VOOutput voltage
V
IOHHigh-level output current
IOLLow-level output current
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414D – APRIL 1998 – REVISED JANUARY 2000
recommended operating conditions (see Note 4)
SN54LV595A SN74LV595A
MIN MAX MIN MAX
V
V
∆t/∆v Input transition rise or fall rate
T
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5.5 2 5.5 V
CC
VCC = 2 V 1.5 1.5
p
p
Input voltage 0 5.5 0 5.5 V
I
p
p
p
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
VCC = 2.3 V to 2.7 V VCC× 0.7 VCC× 0.7
VCC = 3 V to 3.6 V VCC× 0.7 VCC× 0.7
VCC = 4.5 V to 5.5 V VCC× 0.7 VCC× 0.7
VCC = 2 V 0.5 0.5
VCC = 2.3 V to 2.7 V VCC× 0.3 VCC× 0.3
VCC = 3 V to 3.6 V VCC× 0.3 VCC× 0.3
VCC = 4.5 V to 5.5 V VCC× 0.3 VCC× 0.3
High or low state 0 V
3-state 0 5.5 0 5.5
VCC = 2 V –50 –50 µA
VCC = 2.3 V to 2.7 V –2 –2
VCC = 3 V to 3.6 V –8 –8
VCC = 4.5 V to 5.5 V –16 –16
VCC = 2 V 50 50 µA
VCC = 2.3 V to 2.7 V 2 2
VCC = 3 V to 3.6 V 8 8
VCC = 4.5 V to 5.5 V 16 16
VCC = 2.3 V to 2.7 V 0 200 0 200
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V 0 20 0 20
, literature number SCBA004.
0 100 0 100
CC
0 V
CC
mA
mA
ns/V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
V
UNIT
V
3 V
V
4.5 V
V
3 V
V
4.5 V
CiV
V
or GND
pF
UNIT
t
Set
ns
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414D – APRIL 1998 – REVISED JANUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV595A SN74LV595A
MIN TYP MAX MIN TYP MAX
2.48 2.48
2.48 2.48
3.8 3.8
3.8 3.8
0.44 0.44
0.44 0.44
0.55 0.55
0.55 0.55
p
I
I
I
I
OH
OL
I
OZ
CC
off
Q
H′
QA–Q
Q
H′
QA–Q
Q
H′
QA–Q
Q
H′
QA–Q
CC
IOH = –50 µA 2 V to 5.5 V VCC–0.1 VCC–0.1
IOH = –2 mA 2.3 V 2 2
IOH = –6 mA
IOH = –8 mA
H
IOH = –12 mA
IOH = –16 mA
H
IOL = 50 µA 2 V to 5.5 V 0.1 0.1
IOL = 2 mA 2.3 V 0.4 0.4
IOL = 6 mA
IOL = 8 mA
H
IOL = 12 mA
IOL = 16 mA
H
VI = VCC or GND 5.5 V ±1 ±1 µA
VO = VCC or GND 5.5 V ±5 ±5 µA
VI = VCC or GND IO = 0 5.5 V 20 20 µA
VI or VO = 0 to 5.5 V 0 V 5 5 µA
=
I
CC
3.3 V 3.5 3.5
5 V 3 3
timing requirements over recommended operating free-air temperature range, V
= 2.5 V ± 0.2 V
CC
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV595A SN74LV595A
MIN MAX MIN MAX MIN MAX
SRCLK high or low 7 7.5 7.5
t
w
su
t
h
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together , in which case the shift
register is one clock pulse ahead of the storage register.
Pulse duration
up time
Hold time SER after SRCLK↑ 1.5 1.5 1.5 ns
RCLK high or low
SRCLR low 6 6.5 6.5
SER before SRCLK↑ 2.5 3 3
SRCLK↑ before RCLK↑
low before RCLK↑ 8.5 9.5 9.5
SRCLR
SRCLR high (inactive) before SRCLK↑ 4 4 4
†
7 7.5 7.5
8 9 9
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN54LV595A, SN74LV595A
UNIT
t
Set
ns
UNIT
t
Set
ns
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414D – APRIL 1998 – REVISED JANUARY 2000
timing requirements over recommended operating free-air temperature range, V
= 3.3 V ± 0.3 V
CC
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV595A SN74LV595A
MIN MAX MIN MAX MIN MAX
SRCLK high or low 5.5 5.5 5.5
t
w
su
t
h
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together , in which case the shift
register is one clock pulse ahead of the storage register.
timing requirements over recommended operating free-air temperature range, V
Pulse duration
up time
Hold time SER after SRCLK↑ 1.5 1.5 1.5 ns
RCLK high or low
SRCLR low 5 5 5
SER before SRCLK↑ 3.5 3.5 3.5
SRCLK↑ before RCLK↑
low before RCLK↑ 8 9 9
SRCLR
SRCLR high (inactive) before SRCLK↑ 3 3 3
†
5.5 5.5 5.5
8 8.5 8.5
= 5 V ± 0.5 V
CC
ns
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV595A SN74LV595A
MIN MAX MIN MAX MIN MAX
SRCLK high or low 5 5 5
t
w
su
t
h
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together , in which case the shift
register is one clock pulse ahead of the storage register.
Pulse duration
up time
Hold time SER after SRCLK↑ 2 2 2 ns
RCLK high or low
SRCLR low 5.2 5.2 5.2
SER before SRCLK↑ 3 3 3
SRCLK↑ before RCLK↑
SRCLR
low before RCLK↑ 5 5 5
SRCLR high (inactive) before SRCLK↑ 2.5 2.5 2.5
†
5 5 5
5 5 5
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
UNIT
f
MH
RCLK
Q
Q
SRCLK
Q
OE
Q
Q
OE
Q
Q
RCLK
Q
Q
SRCLK
Q
OE
Q
Q
OE
Q
Q
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414D – APRIL 1998 – REVISED JANUARY 2000
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
t
*
PLH
t
*
PHL
t
*
PLH
t
*
PHL
t
*
PHL
t
*
PZH
t
*
PZL
t
*
PHZ
t
*
PLZ
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
SRCLR Q
SRCLR Q
–
A
H
H′
H′
–
A
H
–
A
H
–
A
H
H′
H′
–
A
H
–
A
H
CL = 15 pF* 65 80 45 45
CL = 50 pF 60 70 40 40
CL = 15 pF
CL = 50 pF
TA = 25°C SN54LV595A SN74LV595A
MIN TYP MAX MIN MAX MIN MAX
8.4 14.2 1 15.8 1 15.8
8.4 14.2 1 15.8 1 15.8
9.4 19.6 1 22.2 1 22.2
9.4 19.6 1 22.2 1 22.2
8.7 14.6 1 16.3 1 16.3
8.2 13.9 1 15 1 15
10.9 18.1 1 20.3 1 20.3
8.3 13.7 1 15.6 1 15.6
9.2 15.2 1 16.7 1 16.7
11.2 17.2 1 19.3 1 19.3
11.2 17.2 1 19.3 1 19.3
13.1 22.5 1 25.5 1 25.5
13.1 22.5 1 25.5 1 25.5
12.4 18.8 1 21.1 1 21.1
10.8 17 1 18.3 1 18.3
13.4 21 1 23 1 23
12.2 18.3 1 19.5 1 19.5
14 20.9 1 22.6 1 22.6
z
ns
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
SN54LV595A, SN74LV595A
PARAMETER
UNIT
f
MH
RCLK
Q
Q
SRCLK
Q
OE
Q
Q
OE
Q
Q
RCLK
Q
Q
SRCLK
Q
OE
Q
Q
OE
Q
Q
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414D – APRIL 1998 – REVISED JANUARY 2000
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
t
*
PLH
t
*
PHL
t
*
PLH
t
*
PHL
t
*
PHL
t
*
PZH
t
*
PZL
t
*
PHZ
t
*
PLZ
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
SRCLR Q
SRCLR Q
–
A
H
H′
H′
–
A
H
–
A
H
–
A
H
H′
H′
–
A
H
–
A
H
CL = 15 pF* 80 120 70 70
CL = 50 pF 55 105 50 50
CL = 15 pF
CL = 50 pF
TA = 25°C SN54LV595A SN74LV595A
MIN TYP MAX MIN MAX MIN MAX
6 11.9 1 13.5 1 13.5
6 11.9 1 13.5 1 13.5
6.6 13 1 15 1 15
6.6 13 1 15 1 15
6.2 12.8 1 13.7 1 13.7
6 11.5 1 13.5 1 13.5
7.8 11.5 1 13.5 1 13.5
6.1 14.7 1 15.2 1 15.2
6.3 14.7 1 15.2 1 15.2
7.9 15.4 1 17 1 17
7.9 15.4 1 17 1 17
9.2 16.5 1 18.5 1 18.5
9.2 16.5 1 18.5 1 18.5
9 16.3 1 17.2 1 17.2
7.8 15 1 17 1 17
9.6 15 1 17 1 17
8.1 15.7 1 16.2 1 16.2
9.3 15.7 1 16.2 1 16.2
z
ns
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
UNIT
f
MH
RCLK
Q
Q
SRCLK
Q
OE
Q
Q
OE
Q
Q
RCLK
Q
Q
SRCLK
Q
OE
Q
Q
OE
Q
Q
PARAMETER
UNIT
C
d
Power dissi ation ca acitance
C
L
MHz
F
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414D – APRIL 1998 – REVISED JANUARY 2000
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
t
*
PLH
t
*
PHL
t
*
PLH
t
*
PHL
t
*
PHL
t
*
PZH
t
*
PZL
t
*
PHZ
t
*
PLZ
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
SRCLR Q
SRCLR Q
–
A
H
H′
H′
–
A
H
–
A
H
–
A
H
H′
H′
–
A
H
–
A
H
CL = 15 pF* 135 170 115 115
CL = 50 pF 120 140 95 95
CL = 15 pF
CL = 50 pF
TA = 25°C SN54LV595A SN74LV595A
MIN TYP MAX MIN MAX MIN MAX
4.3 7.4 1 8.5 1 8.5
4.3 7.4 1 8.5 1 8.5
4.5 8.2 1 9.4 1 9.4
4.5 8.2 1 9.4 1 9.4
4.5 8 1 9.1 1 9.1
4.3 8.6 1 10 1 10
5.4 8.6 1 10 1 10
2.4 6 1 7.1 1 7.1
2.7 5.1 1 7.2 1 7.2
5.6 9.4 1 10.5 1 10.5
5.6 9.4 1 10.5 1 10.5
6.4 10.2 1 11.4 1 11.4
6.4 10.2 1 11.4 1 11.4
6.4 10 1 11.1 1 11.1
5.7 10.6 1 12 1 12
6.8 10.6 1 12 1 12
3.5 10.3 1 11 1 11
3.4 10.3 1 11 1 11
z
ns
ns
noise characteristics, V
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
NOTE 5: Characteristics are for surface-mount packages only.
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage 2.31 V
Low-level dynamic input voltage 0.99 V
= 3.3 V, C
CC
= 50 pF, TA = 25°C (see Note 5)
L
OL
OL
OH
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS V
p
p
p
p
= 50 F,f = 10
SN74LV595A
MIN TYP MAX
0.3 V
–0.2 V
2.8 V
TYP UNIT
CC
3.3 V 111
5 V 114
p
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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11
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414D – APRIL 1998 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
(see Note A)
Test
Point
C
L
From Output
Under Test
(see Note A)
V
RL = 1 kΩ
C
L
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
t
w
Input
Input
In-Phase
Output
Out-of-Phase
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
F. t
G. t
50% V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
50% V
CC
t
PLH
50% V
CC
t
PHL
50% V
CC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
PLZ
PZL
PHL
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PLH
3-STATE AND OPEN-DRAIN OUTPUTS
50% V
50% V
dis
CC
t
PHL
50% V
t
PLH
50% V
.
LOAD CIRCUIT FOR
V
CC
CC
0 V
V
CC
0 V
V
OH
CC
V
OL
V
OH
CC
V
OL
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Waveform 2
(see Note B)
CC
Output
S1 at GND
50% V
CC
t
CC
CC
h
50% V
50% V
CC
CC
VOL + 0.3 V
VOH – 0.3 V
t
su
50% V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
50% V
CC
t
PZL
50% V
t
PZH
50% V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
t
PLZ
t
PHZ
V
CC
0 V
V
CC
0 V
V
CC
0 V
≈ V
V
OL
V
OH
≈ 0 V
CC
12
Figure 1. Load Circuit and Voltage Waveforms
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