Texas Instruments SN74LV595AD, SN74LV595ADBR, SN74LV595ADR, SN74LV595APWR Datasheet
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414D – APRIL 1998 – REVISED JANUARY 2000
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Typical V
(Output Ground Bounce)
OLP
<0.8 V at VCC = 3.3 V, TA = 25°C
D
T ypical V
at V
D
8-Bit Serial-In, Parallel-Out Shift
D
Shift Register Has Direct Clear
D
Latch-Up Performance Exceeds 250 mA Per
= 3.3 V, TA = 25°C
CC
(Output VOH Undershoot) >2 V
OHV
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Flat (W) Packages, Chip
Carriers (FK), and DIPs (J)
description
The ’LV595A devices are 8-bit shift registers
designed for 2-V to 5.5-V VCC operation.
These devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. The storage register has parallel
3-state outputs. Separate clocks are provided for
both the shift and storage register. The shift
register has a direct overriding clear (SRCLR
input, serial (SER) input, and a serial output for
cascading. When the output-enable (OE) input is
high, all outputs except QH′ are in the
high-impedance state.
SN54LV595A...J OR W PACKAGE
SN74LV595A. . . D, DB, NS, OR PW PACKAGE
SN54LV595A. . . FK PACKAGE
Q
D
Q
E
NC
Q
F
Q
G
NC – No internal connection
(TOP VIEW)
Q
1
B
Q
2
C
Q
3
D
Q
4
E
5
Q
F
6
Q
G
7
Q
H
GND
8
(TOP VIEW)
CQB
Q
3212019
4
5
6
7
8
910111213
H
Q
NC
GND
16
15
14
13
12
11
10
NC
9
VCCQ
′
H
Q
V
CC
Q
A
SER
OE
RCLK
SRCLK
SRCLR
Q
H′
A
SER
18
OE
17
NC
16
RCLK
15
14
SRCLK
SRCLR
)
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both
clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54L V595A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV595A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
SN54LV595A, SN74LV595A
FUNCTION
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414D – APRIL 1998 – REVISED JANUARY 2000
INPUTS
SER SRCLK SRCLR RCLK OE
X X X X H Outputs QA–QH are disabled.
X X X X L Outputs QA–QH are enabled.
X X L X X Shift register is cleared.
L ↑ H X X
H ↑ H X X
X ↓ H X X Shift-register state is not changed.
X XX↑ X Shift-register data is stored into the storage register.
X X X ↓ X Storage-register state is not changed.
FUNCTION TABLE
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, NS, PW, and W packages.
†
OE
RCLK
SRCLR
SRCLK
SER
13
12
10
11
14
EN3
R
1D
C2
SRG8
C1/
2D
2D
15
3
3
Q
A
1
Q
B
2
Q
C
3
Q
D
4
Q
E
5
Q
F
6
Q
G
7
Q
H
9
Q
H′
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
13
OE
SER
12
10
11
14
RCLK
SRCLR
SRCLK
1D
R
C1
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414D – APRIL 1998 – REVISED JANUARY 2000
Q
3D
C3
Q
15
Q
A
2D
R
2D
R
2D
R
2D
R
2D
R
2D
R
C2
C2
C2
C2
C2
C2
Q
Q
Q
Q
Q
Q
3D
3D
3D
3D
3D
3D
C3
C3
C3
C3
C3
C3
Q
Q
Q
Q
Q
Q
1
Q
B
2
Q
C
3
Q
D
4
Q
E
5
Q
F
6
Q
G
2D
C2
R
Pin numbers shown are for the D, DB, J, NS, PW, and W packages.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Q
3D
C3
7
Q
Q
H
9
Q
H′
3
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414D – APRIL 1998 – REVISED JANUARY 2000
timing diagram
SRCLK
SER
RCLK
SRCLR
OE
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
Q
H’
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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