Texas Instruments SN74LV594ADR, SN74LV594ANSR, SN74LV594APWR, SN74LV594AD, SN74LV594ADBR Datasheet
SN54LV594A, SN74LV594A
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS413B – APRIL 1998 – REVISED SEPTEMBER 1999
D
EPIC
(Enhanced-Performance
Implanted CMOS) Process
D
Typical V
(Output Ground Bounce)
OLP
<0.8 V at VCC = 3.3 V, TA = 25°C
D
Typical V
>2 V at V
D
8-Bit Serial-In, Parallel-Out Shift
(Output VOH Undershoot)
OHV
= 3.3 V, TA = 25°C
CC
Registers With Storage
D
Independent Direct Overriding Clears
on Shift and Storage Registers
D
Independent Clocks for Shift and
Storage Registers
D
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D
Package Options Include Plastic
Small-Outline (D, NS), Shrink
Small-Outline (DB), and Thin Shrink
Small-Outline (PW) Packages, Ceramic
Flat (W) Packages, Chip Carriers (FK),
and DIPs (J)
description
The ’LV594A devices are 8-bit shift registers
designed for 2-V to 5.5-V VCC operation.
SN54LV594A...J OR W PACKAGE
SN74LV594A. . . D, DB, NS, OR PW PACKAGE
SN54LV594A. . . FK PACKAGE
Q
D
Q
E
NC
Q
F
Q
G
NC – No internal connection
(TOP VIEW)
Q
1
B
Q
2
C
Q
3
D
Q
4
E
5
Q
F
6
Q
G
7
Q
H
GND
8
(TOP VIEW)
CQB
Q
3212019
4
5
6
7
8
910111213
H
Q
NC
NC
GND
16
15
14
13
12
11
10
9
VCCQ
′
H
Q
V
CC
Q
A
SER
RCLR
RCLK
SRCLK
SRCLR
Q
H′
A
SER
18
RCLR
17
NC
16
RCLK
15
14
SRCLK
SRCLR
These devices contain an 8-bit serial-in, parallelout shift register that feeds an 8-bit D-type storage
register. Separate clocks (RCLK, SRCLK) and
direct overriding clear (RCLR, SRCLR) inputs are provided on the shift and storage registers. A serial output
(QH′) is provided for cascading purposes.
The shift-register (SRCLK) and storage-register (RCLK) clocks are positive-edge triggered. If the clocks are tied
together, the shift register always is one clock pulse ahead of the storage register.
The SN54LV594A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LV594A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Copyright 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54LV594A, SN74LV594A
FUNCTION
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS413B – APRIL 1998 – REVISED SEPTEMBER 1999
INPUTS
SER SRCLK SRCLR RCLK RCLR
X X L X X Shift register is cleared.
L ↑ HXX
H ↑ HXX
L
X X X X L Storage register is cleared.
X XX↑ H Shift register data is stored in the storage register.
X X X
#
H X X Shift register state is not changed.
FUNCTION TABLE
First stage of shift register goes low. Other stages
store the data of previous stage, respectively.
First stage of shift register goes high. Other stages
store the data of previous stage, respectively.
#
H Storage register state is not changed.
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, NS, PW, and W packages.
†
SER
13
12
10
11
14
RCLR
RCLK C2
SRCLR
SRCLK
R3
R
1D
SRG8
C1/
2D
2D
15
3
3
Q
A
1
Q
B
2
Q
C
3
Q
D
4
Q
E
5
Q
F
6
Q
G
7
Q
H
9
Q
H′
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
SN54LV594A, SN74LV594A
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS413B – APRIL 1998 – REVISED SEPTEMBER 1999
RCLR
RCLK
SRCLR
SRCLK
SER
13
12
10
11
14
1D
R
2D
R
2D
R
2D
R
C1
C2
C2
C2
Q
Q
Q
Q
R
3D
R
3D
R
3D
R
3D
Q
C3
Q
C3
Q
C3
Q
C3
15
Q
A
1
Q
B
2
Q
C
3
Q
D
2D
C2
R
2D
C2
R
2D
C2
R
2D
C2
R
Pin numbers shown are for the D, DB, J, NS, PW, and W packages.
Q
Q
Q
Q
R
3D
R
3D
R
3D
R
3D
Q
C3
Q
C3
Q
C3
Q
C3
4
Q
E
5
Q
F
6
Q
G
7
Q
H
9
Q
H′
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54LV594A, SN74LV594A
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS413B – APRIL 1998 – REVISED SEPTEMBER 1999
timing diagram
SRCLK
SER
RCLK
SRCLR
RCLR
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
Q
H’
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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