Texas Instruments SN74LV573DBLE, SN74LV573DBR, SN74LV573DW, SN74LV573DWR, SN74LV573PWLE Datasheet
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SN54LV573, SN74LV573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS198B – FEBRUARY 1993 – REVISED APRIL 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
EPIC
(Enhanced-Performance Implanted
CMOS) 2-µ Process
D
T ypical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
, TA = 25°C
D
T ypical V
OHV
(Output VOH Undershoot)
> 2 V at VCC, TA = 25°C
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
description
These octal transparent D-type latches are
designed for 2.7-V to 5.5-V VCC operation.
The ’LV573 feature 3-state outputs designed
specifically for driving highly capacitive or
relatively low-impedance loads. This device is
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the
Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly . The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE
does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN74L V573 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54L V573 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV573 is characterized for operation from –40°C to 85°C.
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
EPIC is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3212019
910111213
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2D1DOE
8Q
7Q
V
1Q
8D
GND
LE
SN54LV573. . . FK PACKAGE
(TOP VIEW)
CC
SN54LV573. . . J OR W PACKAGE
SN74LV573. . . DB, DW, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
SN54LV573, SN74LV573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS198B – FEBRUARY 1993 – REVISED APRIL 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
OE LE D
Q
L H H H
L HL L
L LX Q
0
H X X Z
logic symbol
†
logic diagram (positive logic)
OE
1D
2
1D
3
2D
4
3D
5
4D
6
5D
C1
11
LE
1Q
19
2Q
18
3Q
17
4Q
16
5Q
15
6Q
14
7Q
13
8Q
12
7
6D
8
7D
9
8D
EN
1
OE
LE
1D
1Q
1
11
2
19
To Seven Other Channels
C1
1D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for DB, DW, J, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 3):DB package 0.6 W. . . . . . . . . . . . . . . . . . .
DW package 1.6 W. . . . . . . . . . . . . . . . . .
PW package 0.7 W. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
SN54LV573, SN74LV573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS198B – FEBRUARY 1993 – REVISED APRIL 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
SN54LV573 SN74LV573
MIN MAX MIN MAX
UNIT
V
CC
Supply voltage 2.7 5.5 2.7 5.5 V
p
VCC = 2.7 V to 3.6 V 2 2
VIHHigh-level input voltage
VCC = 4.5 V to 5.5 V 3.15 3.15
V
p
VCC = 2.7 V to 3.6 V 0.8 0.8
VILLow-level input voltage
VCC = 4.5 V to 5.5 V 1.65 1.65
V
V
I
Input voltage 0 V
CC
0 V
CC
V
O
Output voltage 0 V
CC
0 V
CC
V
p
VCC = 2.7 V to 3.6 V –8 –8
IOHHigh-level output current
VCC = 4.5 V to 5.5 V –16 –16
mA
p
VCC = 2.7 V to 3.6 V 8 8
IOLLow-level output current
VCC = 4.5 V to 5.5 V 16 16
mA
∆t/∆v Input transition rise or fall rate 0 100 0 100 ns/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV573 SN74LV573
PARAMETER
TEST CONDITIONS
V
CC
†
MIN TYP MAX MIN TYP MAX
UNIT
IOH = –100 µA MIN to MAX VCC–0.2 VCC–0.2
V
OH
IOH = – 8 mA 3 V 2.4 2.4
V
IOH = – 16 mA 4.5 V 3.6 3.6
IOL = 100 µA MIN to MAX 0.2 0.2
V
OL
IOL = 8 mA 3 V 0.4 0.4
V
IOL = 16 mA 4.5 V 0.55 0.55
3.6 V ±1 ±1
I
I
V
I
=
V
CC
or
GND
5.5 V ±1 ±1
µ
A
3.6 V ±5 ±5
I
OZ
V
O
=
V
CC
or
GND
5.5 V ±5 ±5
µ
A
3.6 V 20 20
I
CC
V
I
=
V
CC
or
GND
,
I
O
=
0
5.5 V 20 20
µ
A
n
I
CC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
3 V to 3.6 V 500 500 µA
3.3 V 2.5 2.5
p
C
i
V
I
=
V
CC
or GND
5 V 3 3
pF
3.3 V 7 7
p
C
o
V
O
=
V
CC
or
GND
5 V 10 10
F
†
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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