Texas Instruments SN74LV573ADBR, SN74LV573ADGVR, SN74LV573ADW, SN74LV573ADWR, SN74LV573APWR Datasheet
SN54LV573A, SN74LV573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS41 1B – APRIL 1998 – REVISED SEPTEMBER 1998
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Typical V
< 0.8 V at V
D
Typical V
> 2 V at V
D
Latch-Up Performance Exceeds 250 mA
(Output Ground Bounce)
OLP
= 3.3 V , TA = 25°C
CC
(Output VOH Undershoot)
OHV
= 3.3 V , TA = 25°C
CC
Per JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (DW, NS), Shrink
Small-Outline (DB), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Flat (W) Packages, Chip
Carriers (FK), and DIPs (J)
description
The ’L V573A devices are octal transparent D-type
latches designed for 2-V to 5.5-V V
These devices feature 3-state outputs designed
specifically for driving highly capacitive or
relatively low-impedance loads. This device is
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
CC
operation.
SN74LV573A. . . DB, DGV, DW, NS, OR PW PACKAGE
SN54LV573A...J OR W PACKAGE
(TOP VIEW)
OE
1
1D
2
2D
3
3D
4
4D
5
5D
6
6D
7
7D
8
9
8D
GND
SN54LV573A. . . FK PACKAGE
3D
4D
5D
6D
7D
10
(TOP VIEW)
2D1DOE
3212019
4
5
6
7
8
910111213
8D
GND
LE
20
19
18
17
16
15
14
13
12
11
V
8Q
CC
V
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
18
17
16
15
14
7Q 1Q
CC
2Q
3Q
4Q
5Q
6Q
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the
Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE
) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly . The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE
does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54LV573A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LV573A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Copyright 1998, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54LV573A, SN74LV573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS41 1B – APRIL 1998 – REVISED SEPTEMBER 1998
FUNCTION TABLE
INPUTS
OE LE D
L H H H
L HL L
LLX Q
HXX Z
(each latch)
OUTPUT
Q
0
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
OE
LE
1D
2D
3D
4D
5D
6D
7D
8D
1
11
2
3
4
5
6
7
8
9
EN
C1
1D
logic diagram (positive logic)
1
OE
11
LE
C1
1D
1D
2
19
18
17
16
15
14
13
12
19
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1Q
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV573A, SN74LV573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS41 1B – APRIL 1998 – REVISED SEPTEMBER 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
Output voltage range applied in the high or low state, V
Output voltage range applied in high-impedance or power-off state, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
Storage temperature range, T
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . .
O
(see Note 1) –0.5 V to 7 V. . . . . . .
O
DGV package 146°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 100°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
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3
SN54LV573A, SN74LV573A
UNIT
VIHHigh-level input voltage
V
VILLow-level input voltage
V
VOOutput voltage
V
IOHHigh-level output current
IOLLow-level output current
PARAMETER
TEST CONDITIONS
V
UNIT
V
V
V
V
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS41 1B – APRIL 1998 – REVISED SEPTEMBER 1998
recommended operating conditions (see Note 4)
SN54LV573A SN74LV573A
MIN MAX MIN MAX
V
V
∆t/∆v Input transition rise or fall rate
T
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5.5 2 5.5 V
CC
VCC = 2 V 1.5 1.5
p
p
Input voltage 0 5.5 0 5.5 V
I
p
p
p
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
VCC = 2.3 V to 2.7 V VCC× 0.7 VCC× 0.7
VCC = 3 V to 3.6 V VCC× 0.7 VCC× 0.7
VCC = 4.5 V to 5.5 V VCC× 0.7 VCC× 0.7
VCC = 2 V 0.5 0.5
VCC = 2.3 V to 2.7 V VCC× 0.3 VCC× 0.3
VCC = 3 V to 3.6 V VCC× 0.3 VCC× 0.3
VCC = 4.5 V to 5.5 V VCC× 0.3 VCC× 0.3
High or low state 0 V
3-state 0 5.5 0 5.5
VCC = 2 V –50 –50 µA
VCC = 2.3 V to 2.7 V –2 –2
VCC = 3 V to 3.6 V –8 –8
VCC = 4.5 V to 5.5 V –16 –16
VCC = 2 V 50 50 µA
VCC = 2.3 V to 2.7 V 2 2
VCC = 3 V to 3.6 V 8 8
VCC = 4.5 V to 5.5 V 16 16
VCC = 2.3 V to 2.7 V 0 200 0 200
VCC = 3 V to 3.6 V 0 100 0 100
VCC = 4.5 V to 5.5 V 0 20 0 20
, literature number SCBA004.
CC
0 V
CC
mA
mA
ns/V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
I
I
I
OZ
I
CC
I
off
C
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
OH
OL
i
CC
IOH = –50 µA 2 V to 5.5 V VCC–0.1 VCC–0.1
IOH = –2 mA 2.3 V 2 2
IOH = –8 mA 3 V 2.48 2.48
IOH = –16 mA 4.5 V 3.8 3.8
IOL = 50 µA 2 V to 5.5 V 0.1 0.1
IOL = 2 mA 2.3 V 0.4 0.4
IOL = 8 mA 3 V 0.44 0.44
IOL = 16 mA 4.5 V 0.55 0.55
VI = VCC or GND 5.5 V ±1 ±1 µA
VO = VCC or GND 5.5 V ±5 ±5 µA
VI = VCC or GND, IO = 0 5.5 V 20 20 µA
VI or VO = 0 to 5.5 V 0 V 5 5 µA
VI = VCC or GND 3.3 V 1.8 1.8 pF
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SN54LV573A SN74LV573A
MIN TYP MAX MIN TYP MAX
PARAMETER
UNIT
PARAMETER
UNIT
PARAMETER
UNIT
PARAMETER
UNIT
t
d
C
L
F
ns
t
d
SN54LV573A, SN74LV573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS41 1B – APRIL 1998 – REVISED SEPTEMBER 1998
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV573A SN74LV573A
MIN MAX MIN MAX MIN MAX
t
w
t
su
t
h
Pulse duration LE high 6.5 6.5 6.5 ns
Setup time
Hold time
Data before LE↓ 5 5 5 ns
Data after LE↓ 2 2 2 ns
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV573A SN74LV573A
MIN MAX MIN MAX MIN MAX
t
w
t
su
t
h
Pulse duration LE high 5 5 5 ns
Setup time
Hold time
Data before LE↓ 3.5 3.5 3.5 ns
Data after LE↓ 1.5 1.5 1.5 ns
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV573A SN74LV573A
MIN MAX MIN MAX MIN MAX
t
w
t
su
t
h
Pulse duration LE high 5 5 5 ns
Setup time
Hold time
Data before LE↓ 3.5 3.5 3.5 ns
Data after LE↓ 1.5 1.5 1.5 ns
= 2.5 V ± 0.2 V
CC
= 3.3 V ± 0.3 V
CC
= 5 V ± 0.5 V
CC
switching characteristics over recommended operating free-air temperature range,
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
*
p
ten*
t
*
dis
p
t
en
t
dis
†
t
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
Skew between any two outputs of the same package switching in the same direction
D
LE
OE
OE
D
LE
OE
OE
Q
Q
Q
Q 6.7 12.6 1 15 1 15
Q
Q
Q
Q 8.6 17.3 1 19 1 19
CL = 50 pF
= 15
p
TA = 25°C SN54LV573A SN74LV573A
MIN TYP MAX MIN MAX MIN MAX
8.9 15.8 1 18 1 18
9.6 16.2 1 19 1 19
9.3 16.2 1 19 1 19
10.9 18.7 1 21 1 21
11.6 19.1 1 23 1 23
11.4 19 1 22 1 22
2 2
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54LV573A, SN74LV573A
PARAMETER
UNIT
t
d
C
L
F
ns
t
d
PARAMETER
UNIT
t
d
C
L
F
ns
t
d
PARAMETER
UNIT
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS41 1B – APRIL 1998 – REVISED SEPTEMBER 1998
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
*
p
ten*
t
*
dis
p
t
en
t
dis
†
t
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
Skew between any two outputs of the same package switching in the same direction
D
LE
OE
OE
D
LE
OE
OE
Q
Q
Q
Q 4.9 11 1 13 1 13
Q
Q
Q
Q 6.2 14.5 1 16.5 1 16.5
CL = 50 pF
= 15
p
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
*
p
ten*
t
*
dis
p
t
en
t
dis
†
t
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
Skew between any two outputs of the same package switching in the same direction
D
LE
OE
OE
D
LE
OE
OE
Q
Q
Q
Q 3.5 7.7 1 9 1 9
Q
Q
Q
Q 4.2 9.7 1 11 1 11
CL = 50 pF
= 15
p
TA = 25°C SN54LV573A SN74LV573A
MIN TYP MAX MIN MAX MIN MAX
6.2 11 1 13 1 13
6.8 11.9 1 14 1 14
6.6 11.5 1 13.5 1 13.5
7.7 14.5 1 16.5 1 16.5
8.2 15.4 1 17.5 1 17.5
8 15 1 17 1 17
1.5 1.5
TA = 25°C SN54LV573A SN74LV573A
MIN TYP MAX MIN MAX MIN MAX
4.3 6.8 1 8 1 8
4.7 7.7 1 9 1 9
4.7 7.7 1 9 1 9
5.3 8.8 1 10 1 10
5.7 9.7 1 11 1 11
5.7 9.7 1 11 1 11
1 1
ns
ns
noise characteristics, V
NOTE 5: Characteristics are for surface-mount packages only.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
= 3.3 V, CL = 50 pF, TA = 25°C (see Note 5)
CC
SN74LV573A
MIN TYP MAX
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage 2.31 V
Low-level dynamic input voltage 0.99 V
OL
OL
OH
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.55 0.8 V
–0.47 –0.8 V
2.93 V
D to Q
CpdPower dissipation capacitance
Outputs enabled
C
pF
LE to Q
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS V
p
p
SN54LV573A, SN74LV573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS41 1B – APRIL 1998 – REVISED SEPTEMBER 1998
TYP UNIT
CC
3.3 V 16
p
p
= 50 pF,f = 10 MHz
L
5 V 18
3.3 V
5 V 21.3
18.2
p
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7
SN54LV573A, SN74LV573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS41 1B – APRIL 1998 – REVISED SEPTEMBER 1998
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
(see Note A)
Test
Point
C
L
From Output
Under Test
(see Note A)
C
L
RL = 1 kΩ
S1
V
CC
GND
Open
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
t
w
Input
Input
In-Phase
Output
Out-of-Phase
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
F. t
G. t
50% V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
50% V
CC
t
PLH
50% V
CC
t
PHL
50% V
CC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
PLZ
PZL
PHL
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PLH
3-STATE AND OPEN-DRAIN OUTPUTS
50% V
50% V
dis
CC
t
PHL
50% V
t
PLH
50% V
.
LOAD CIRCUIT FOR
V
CC
CC
0 V
V
CC
0 V
V
OH
CC
V
OL
V
OH
CC
V
OL
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Waveform 2
(see Note B)
CC
Output
S1 at GND
50% V
CC
t
CC
CC
h
50% V
50% V
CC
CC
VOL + 0.3 V
VOH – 0.3 V
t
su
50% V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
50% V
CC
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
t
PLZ
50% V
t
PHZ
50% V
V
CC
0 V
V
CC
0 V
V
CC
0 V
≈ V
V
OL
V
OH
≈ 0 V
CC
Figure 1. Load Circuit and Voltage Waveforms
8
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Copyright 1998, Texas Instruments Incorporated
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