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SN54LV541A, SN74LV541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS410D – APRIL 1998 – REVISED MA Y 2000
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Typical V
<0.8 V at V
D
Typical V
>2.3 V at V
D
2-V to 5.5-V VCC Operation
D
Support Mixed-Mode Voltage Operation on
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
(Output VOH Undershoot)
OHV
= 3.3 V, TA = 25°C
CC
All Ports
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds 200 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (DW, NS), Shrink
Small-Outline (DB), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Flat (W) Package, Chip
Carriers (FK), and DIPs (J)
description
The ’LV541A devices are octal buffers/drivers
designed for 2-V to 5.5-V VCC operation.
SN74LV541A. . . DB, DGV, DW, NS, OR PW PACKAGE
SN54LV541A...J OR W PACKAGE
(TOP VIEW)
OE1
1
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
9
A8
GND
SN54LV541A. . . FK PACKAGE
A3
A4
A5
A6
A7
10
(TOP VIEW)
A2A1OE1
3212019
4
5
6
7
8
910111213
20
19
18
17
16
15
14
13
12
11
V
CC
V
CC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
18
17
16
15
14
Y1
Y2
Y3
Y4
Y5
These devices are ideal for driving bus lines or
buffer memory address registers. They feature
A8
GND
Y8
Y7
Y6 OE2
inputs and outputs on opposite sides of the
package to facilitate printed circuit board layout.
The 3-state control gate is a two-input AND gate with active-low inputs so that if either output-enable (OE1 or
OE2) input is high, all corresponding outputs are in the high-impedance state. The outputs provide noninverted
data when they are not in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54LV541A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LV541A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer/driver)
INPUTS
OE1 OE2 A
L L L L
L LH H
H XX Z
X H X Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OUTPUT
Y
EPIC is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
SN54LV541A, SN74LV541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS410D – APRIL 1998 – REVISED MA Y 2000
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
OE1
OE2
A1
A2
A3
A4
A5
A6
A7
A8
1
19
2
3
4
5
6
7
8
9
&
EN
1
logic diagram (positive logic)
OE1
OE2
1
19
18
17
16
15
14
13
12
11
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
218
A1
To Seven Other Channels
Y1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, V
Output voltage range applied in the high or low state, V
Input clamp current, IIK (VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(see Note 3): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . .
O
DGV package 92°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
‡
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
VIHHigh-level input voltage
V
VILLow-level input voltage
V
VOOutput voltage
V
IOHHigh-level output current
IOLLow-level output current
PARAMETER
TEST CONDITIONS
V
UNIT
V
V
V
V
SN54LV541A, SN74LV541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS410D – APRIL 1998 – REVISED MA Y 2000
recommended operating conditions (see Note 4)
SN54LV541A SN74LV541A
MIN MAX MIN MAX
V
V
∆t/∆v Input transition rise or fall rate
T
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5.5 2 5.5 V
CC
VCC = 2 V 1.5 1.5
p
p
Input voltage 0 5.5 0 5.5 V
I
p
p
p
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
VCC = 2.3 V to 2.7 V VCC× 0.7 VCC× 0.7
VCC = 3 V to 3.6 V VCC× 0.7 VCC× 0.7
VCC = 4.5 V to 5.5 V VCC× 0.7 VCC× 0.7
VCC = 2 V 0.5 0.5
VCC = 2.3 V to 2.7 V VCC× 0.3 VCC× 0.3
VCC = 3 V to 3.6 V VCC× 0.3 VCC× 0.3
VCC = 4.5 V to 5.5 V VCC× 0.3 VCC× 0.3
High or low state 0 V
3-state 0 5.5 0 5.5
VCC = 2 V –50 –50 µA
VCC = 2.3 V to 2.7 V –2 –2
VCC = 3 V to 3.6 V –8 –8
VCC = 4.5 V to 5.5 V –16 –16
VCC = 2 V 50 50 µA
VCC = 2.3 V to 2.7 V 2 2
VCC = 3 V to 3.6 V 8 8
VCC = 4.5 V to 5.5 V 16 16
VCC = 2.3 V to 2.7 V 0 200 0 200
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V 0 20 0 20
, literature number SCBA004.
0 100 0 100
CC
0 V
CC
mA
mA
ns/V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
I
I
I
I
C
OH
OL
I
OZ
CC
off
i
CC
IOH = –50 µA 2 V to 5.5 V VCC–0.1 VCC–0.1
IOH = –2 mA 2.3 V 2 2
IOH = –8 mA 3 V 2.48 2.48
IOH = –16 mA 4.5 V 3.8 3.8
IOL = 50 µA 2 V to 5.5 V 0.1 0.1
IOL = 2 mA 2.3 V 0.4 0.4
IOL = 8 mA 3 V 0.44 0.44
IOL = 16 mA 4.5 V 0.55 0.55
VI = VCC or GND 0 V to 5.5 V ±1 ±1 µA
VO = VCC or GND 5.5 V ±5 ±5 µA
VI = VCC or GND, IO = 0 5.5 V 20 20 µA
VI or VO = 0 to 5.5 V 0 V 5 5 µA
VI = VCC or GND 3.3 V 2 2 pF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV541A SN74LV541A
MIN TYP MAX MIN TYP MAX
3
SN54LV541A, SN74LV541A
PARAMETER
UNIT
C
F
PARAMETER
UNIT
C
50 pF
PARAMETER
UNIT
C
F
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS410D – APRIL 1998 – REVISED MA Y 2000
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
t
pd
t
en
t
dis
t
pd
t
en
t
dis
t
sk(o)
∗
On products compliant to MIL-PRF-38535, this parameter is not production tested.
A Y 6.7* 11.3* 1* 13.5* 1 13.5
OE
OE
A Y 8.7 15.9 1 18.5 1 18.5
OE
OE
Y
Y 8.4* 13.1* 1* 15* 1 15
Y
Y
CL = 15 pF
= 50 p
L
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
t
pd
t
en
t
dis
t
pd
t
en
t
dis
t
sk(o)
∗
On products compliant to MIL-PRF-38535, this parameter is not production tested.
A Y 4.8* 7* 1* 8.5* 1 8.5
OE
OE
A Y 6.1 10.5 1 12 1 12
OE
OE
Y
Y 5.8* 11* 1* 12* 1 12
Y
Y
CL = 15 pF
=
L
TA = 25°C SN54LV541A SN74LV541A
MIN TYP MAX MIN MAX MIN MAX
8.5* 16.6* 1* 19.5* 1 19.5
10.5 20.7 1 24 1 24
12.3 17.9 1 20 1 20
2 2
TA = 25°C SN54LV541A SN74LV541A
MIN TYP MAX MIN MAX MIN MAX
6.1* 10.5* 1* 12.5* 1 12.5
7.4 14 1 16 1 16
8.8 15.4 1 17.5 1 17.5
1.5 1.5
ns
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
t
pd
t
en
t
dis
t
pd
t
en
t
dis
t
sk(o)
∗
On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
A Y 3.5* 5* 1* 6* 1 6
OE
OE
A Y 4.3 7 1 8 1 8
OE
OE
Y
Y 3.9* 7.5* 1* 8* 1 8
Y
Y
CL = 15 pF
= 50 p
L
TA = 25°C SN54LV541A SN74LV541A
MIN TYP MAX MIN MAX MIN MAX
4.3* 7.2* 1* 8.5* 1 8.5
5.3 9.2 1 10.5 1 10.5
5.6 8.8 1 10 1 10
1 1
ns
ns
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
UNIT
CpdPower dissipation capacitance
Outputs enabled
C
pF
SN54LV541A, SN74LV541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS410D – APRIL 1998 – REVISED MA Y 2000
noise characteristics, V
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
NOTE 5: Characteristics are for surface-mount packages only.
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage 2.31 V
Low-level dynamic input voltage 0.99 V
= 3.3 V, CL = 50 pF, TA = 25°C (see Note 5)
CC
OL
OL
OH
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS V
p
p
SN74LV541A
MIN TYP MAX
0.5 0.8 V
–0.4 –0.8 V
2.9 V
TYP UNIT
CC
p
p
= 50 pF,f = 10 MHz
L
3.3 V 16.3
5 V 17.8
p
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54LV541A, SN74LV541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS410D – APRIL 1998 – REVISED MA Y 2000
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
(see Note A)
Test
Point
C
L
From Output
Under Test
(see Note A)
V
RL = 1 kΩ
C
L
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
t
w
Input
Input
In-Phase
Output
Out-of-Phase
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
F. t
G. t
50% V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
50% V
CC
t
PLH
50% V
CC
t
PHL
50% V
CC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
PLZ
PZL
PHL
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PLH
3-STATE AND OPEN-DRAIN OUTPUTS
50% V
50% V
dis
CC
t
PHL
50% V
t
PLH
50% V
.
LOAD CIRCUIT FOR
V
CC
CC
0 V
V
CC
0 V
V
OH
CC
V
OL
V
OH
CC
V
OL
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Waveform 2
(see Note B)
CC
Output
S1 at GND
50% V
CC
t
CC
CC
h
50% V
50% V
CC
CC
VOL + 0.3 V
VOH – 0.3 V
t
su
50% V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
50% V
CC
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
t
PLZ
50% V
t
PHZ
50% V
V
CC
0 V
V
CC
0 V
V
CC
0 V
≈V
V
OL
V
OH
≈0 V
CC
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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