Texas Instruments SN74LV4040AD, SN74LV4040ADBR, SN74LV4040ADGVR, SN74LV4040ADR, SN74LV4040AN Datasheet
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FUNCTION
SN54LV4040A, SN74LV4040A
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Typical V
(Output Ground Bounce)
OLP
<0.8 V at VCC = 3.3 V, TA = 25°C
D
Typical V
>2.3 V at V
D
High On-Off Output-Voltage Ratio
D
Low Crosstalk Between Switches
D
Individual Switch Controls
D
Extremely Low Input Current
D
Latch-Up Performance Exceeds 100 mA Per
(Output VOH Undershoot)
OHV
= 3.3 V, TA = 25°C
CC
JESD 78, Class II
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip Carriers
(FK), and Standard Ceramic (J) DIPs
description
The ’LV4040A devices are 12-bit asynchronous
binary counters with the outputs of all stages
available externally . A high level at the clear (CLR)
input asynchronously clears the counter and
resets all outputs low. The count is advanced on
a high-to-low transition at the clock (CLK) input.
Applications include time-delay circuits, counter
controls, and frequency-dividing circuits.
SN74LV4040A.. . D, DB, DGV, NS, OR PW PACKAGE
SN54LV4040A...J OR W PACKAGE
(TOP VIEW)
Q
1
L
Q
2
F
Q
3
E
Q
4
G
5
Q
D
6
Q
C
7
Q
B
GND
SN54LV4040A.. . FK PACKAGE
Q
E
Q
G
NC
Q
D
Q
C
NC – No internal connection
8
(TOP VIEW)
F
L
QQNC
3212019
4
5
6
7
8
910111213
B
Q
GND
NC
16
15
14
13
12
11
10
V
Q
9
CC
A
V
Q
Q
Q
Q
CLR
CLK
Q
K
Q
18
17
16
15
14
CLK
CC
K
J
H
I
A
Q
J
Q
H
NC
Q
I
CLR
The SN54LV4040A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LV4040A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
CLK CLR
↑ L No change
↓ L Advance to next stage
X H All outputs L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN54LV4040A, SN74LV4040A
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
†
RCTR12
0
CLR
CLK
11
10
CT=0
CT
11
logic diagram (positive logic)
13
12
14
15
9
Q
A
7
Q
B
6
Q
C
5
Q
D
3
Q
E
2
Q
F
4
Q
G
Q
H
Q
I
Q
J
Q
K
1
Q
L
11
CLR
10
CLK
R
T
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
R
T
2 4 13 12 14 15 1
Q
F
R
T
R
T
Q
G
R
T
953
Q
A
R
T
Q
H
R
T
7
Q
B
R
T
Q
I
R
T
6
Q
C
R
T
Q
J
R
T
Q
D
R
Q
K
Q
E
T
Q
L
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
VIHHigh-level input voltage
V
VILLow-level input voltage
V
IOHHigh-level output current
IOLLow-level output current
SN54LV4040A, SN74LV4040A
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999
absolute maximum ratings over operating free-air temperature range
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
Input clamp current, I
Output clamp current, I
(see Notes 1 and 2) –0.5 V to V
O
(V
IK
I
OK
Continuous output current, I
< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 3): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 4)
SN54LV4040A SN74LV4040A
MIN MAX MIN MAX
V
V
V
∆t/∆v Input transition rise or fall rate
T
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5.5 2 5.5 V
CC
VCC = 2 V 1.5 1.5
p
p
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 V
O
p
p
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
VCC = 2.3 V to 2.7 V VCC× 0.7 VCC× 0.7
VCC = 3 V to 3.6 V VCC× 0.7 VCC× 0.7
VCC = 4.5 V to 5.5 V VCC× 0.7 VCC× 0.7
VCC = 2 V 0.5 0.5
VCC = 2.3 V to 2.7 V VCC× 0.3 VCC× 0.3
VCC = 3 V to 3.6 V VCC× 0.3 VCC× 0.3
VCC = 4.5 V to 5.5 V VCC× 0.3 VCC× 0.3
CC
VCC = 2 V –50 –50 µA
VCC = 2.3 V to 2.7 V –2 –2
VCC = 3 V to 3.6 V –6 –6
VCC = 4.5 V to 5.5 V –12 –12
VCC = 2 V 50 50 µA
VCC = 2.3 V to 2.7 V 2 2
VCC = 3 V to 3.6 V 6 6
VCC = 4.5 V to 5.5 V 12 12
VCC = 2.3 V to 2.7 V 0 200 0 200
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V 0 20 0 20
, literature number SCBA004.
0 100 0 100
0 V
CC
V
mA
mA
ns/V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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