Texas Instruments SN74LV367AD, SN74LV367ADBR, SN74LV367ADGVR, SN74LV367ADR, SN74LV367ANSR Datasheet

SN54LV367A, SN74LV367A

HEX BUFFERS AND LINE DRIVERS

WITH 3-STATE OUTPUTS

SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Process

D

Typical V

(Output Ground Bounce)

OLP

< 0.8 V at VCC = 3.3 V, TA = 25°C

D

Typical V > 2 V at V

D

Latch-Up Performance Exceeds 100 mA Per

(Output VOH Undershoot)

OHV

= 3.3 V, TA = 25°C

CC

JESD 78, Class II

D

ESD Protection Exceeds JESD-22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)

D

Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Chip Carriers (FK), and DIPs (J)

description

The ’LV367A devices are hex buffers and line drivers designed for 2-V to 5.5-V VCC operation. These devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

SN74LV367A. . . D, DB, DGV, NS, OR PW PACKAGE

SN54LV367A...J OR W PACKAGE

(TOP VIEW)

NC

16 15 14 13 12 11 10

9

CC

V

1Y4

V

CC

2OE 2A2 2Y2 2A1 2Y1 1A4 1Y4

2OE

18 17 16 15 14

1A4

2A2 2Y2 NC 2A1 2Y1

1OE

1

1A1

2

1Y1

3

1A2

4 5

1Y2

6

1A3

7

1Y3

GND

SN54LV367A. . . FK PACKAGE

1Y1 1A2

NC 1Y2 1A3

NC – No internal connection

8

(TOP VIEW)

1A1

1OE

3212019

4 5 6 7 8

910111213

1Y3

GND

The ’L V367A devices are organized as dual 4-line and 2-line buffers/drivers with active-low output-enable (1OE and 2OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

T o ensure the high-impedance state during power up or power down, OE should be tied to V

through a pullup

CC

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54L V367A is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74LV367A is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each buffer/driver)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

INPUTS

OE A

L H H L LL

H X Z

OUTPUT

Y

Copyright  1999, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN54LV367A, SN74LV367A HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.

†

1OE

1A1 1A2 1A3 1A4

2OE

2A1 2A2

1

2 4 6 10

15

12 14

EN

logic diagram (positive logic)

1OE

1

2OE

15

11 13

3

1Y1

5

1Y2

7

1Y3

9

1Y4

2Y1 2Y2

23

1A1

To Three Other Channels

Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.

1Y1

12 11

2A1

To One Other Channel

2Y1

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LV367A, SN74LV367A

HEX BUFFERS AND LINE DRIVERS

WITH 3-STATE OUTPUTS

SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range applied in the high or low state, V

Output voltage range applied in high-impedance or power-off state, VO (see Note 1) –0.5 V to 7 V. . . . . . .

Input clamp current, IIK (VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through V

or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

Package thermal impedance, θJA (see Note 3): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 7 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . .

O

†

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3

SN54LV367A, SN74LV367A

UNIT

VIHHigh-level input voltage

V

VILLow-level input voltage

V

VOOutput voltage

V

IOHHigh-level output current

IOLLow-level output current

HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999

recommended operating conditions (see Note 4)

SN54LV367A SN74LV367A

MIN MAX MIN MAX

V

∆t/∆v Input transition rise or fall rate

T

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2 5.5 2 5.5 V

CC

VCC = 2 V 1.5 1.5

p

Input voltage 0 5.5 0 5.5 V

I

p

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

VCC = 2.3 V to 2.7 V VCC× 0.7 VCC× 0.7 VCC = 3 V to 3.6 V VCC× 0.7 VCC× 0.7 VCC = 4.5 V to 5.5 V VCC× 0.7 VCC× 0.7 VCC = 2 V 0.5 0.5 VCC = 2.3 V to 2.7 V VCC× 0.3 VCC× 0.3 VCC = 3 V to 3.6 V VCC× 0.3 VCC× 0.3 VCC = 4.5 V to 5.5 V VCC× 0.3 VCC× 0.3

High or low state 0 V 3-state 0 5.5 0 5.5 VCC = 2 V –50 –50 µA VCC = 2.3 V to 2.7 V –2 –2 VCC = 3 V to 3.6 V –8 –8 VCC = 4.5 V to 5.5 V –16 –16 VCC = 2 V 50 50 µA VCC = 2.3 V to 2.7 V 2 2 VCC = 3 V to 3.6 V 8 8 VCC = 4.5 V to 5.5 V 16 16 VCC = 2.3 V to 2.7 V 0 200 0 200 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 20 0 20

, literature number SCBA004.

0 100 0 100

CC

0 V

CC

mA

ns/V

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER

TEST CONDITIONS

V

UNIT

V

PARAMETER

UNIT

PARAMETER

UNIT

SN54LV367A, SN74LV367A

HEX BUFFERS AND LINE DRIVERS

WITH 3-STATE OUTPUTS

SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

SN54LV367A SN74LV367A

MIN TYP MAX MIN TYP MAX

I I I I C C

OH

OL

I OZ CC off

i o

CC

IOH = –50 µA 2 V to 5.5 V VCC–0.1 VCC–0.1 IOH = –2 mA 2.3 V 2 2 IOH = –8 mA 3 V 2.48 2.48 IOH = –16 mA 4.5 V 3.8 3.8 IOL = 50 µA 2 V to 5.5 V 0.1 0.1 IOL = 2 mA 2.3 V 0.4 0.4 IOL = 8 mA 3 V 0.44 0.44 IOL = 16 mA 4.5 V 0.55 0.55 VI = VCC or GND 5.5 V ±1 ±1 µA VO = VCC or GND 5.5 V ±5 ±5 µA VI = VCC or GND, IO = 0 5.5 V 20 20 µA VI or VO = 0 to 5.5 V 0 V 5 5 µA VI = VCC or GND 3.3 V 3 3 pF VI = VCC or GND 3.3 V 5.2 5.2 pF

switching characteristics over recommended operating free-air temperature range,

= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)

V

CC

FROM TO LOAD

(INPUT) (OUTPUT) CAPACITANCE

tpd* A Y 6.4 12.7 1 16 1 16 ten* t

*

dis

t

pd

t

en

t

dis

t

sk(o)

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

OE OE

A Y 8.6 17.5 1 21 1 21 OE OE

Y Y 6.4 14.9 1 20 1 20

Y Y 10.1 19.7 1 25 1 25

CL = 15 pF

CL = 50 pF

CL = 50 pF 2 2 ns

TA = 25°C SN54LV367A SN74LV367A

MIN TYP MAX MIN MAX MIN MAX

6.9 14.9 1 20 1 20

9.4 19.7 1 25 1 25

switching characteristics over recommended operating free-air temperature range,

= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)

V

CC

FROM TO LOAD

(INPUT) (OUTPUT) CAPACITANCE

tpd* A Y 4.7 8.3 1 10 1 10 ten* t

*

dis

t

pd

t

en

t

dis

t

sk(o)

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

OE OE

A Y 6.2 11.8 1 13.5 1 13.5 OE OE

Y Y 4.9 10.5 1 12.5 1 12.5

Y Y 7.3 13.6 1 15.5 1 15.5

CL = 15 pF

CL = 50 pF

CL = 50 pF 1.5 1.5 ns

TA = 25°C SN54LV367A SN74LV367A

MIN TYP MAX MIN MAX MIN MAX

5.1 10.5 1 12.5 1 12.5

6.8 14 1 16 1 16

ns

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

SN54LV367A, SN74LV367A

PARAMETER

UNIT

PARAMETER

UNIT

CpdPower dissipation capacitance

C

pF

HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999

switching characteristics over recommended operating free-air temperature range, V

= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

CC

FROM TO LOAD

(INPUT) (OUTPUT) CAPACITANCE

tpd* A Y 3.6 5.9 1 7 1 7 ten* t

*

dis

t

pd

t

en

t

dis

t

sk(o)

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

OE OE

A Y 4.5 7.9 1 9 1 9 OE OE

Y Y 2.6 7.2 1 8.5 0 8.5

Y Y 4.5 9.2 1 10.5 0 10.5

CL = 15 pF

CL = 50 pF

CL = 50 pF 1 1 ns

TA = 25°C SN54LV367A SN74LV367A

MIN TYP MAX MIN MAX MIN MAX

3.8 7.2 1 8.5 1 8.5

4.9 9.2 1 10.5 1 10.5

ns

noise characteristics, V

V

OL(P)

V

OL(V)

V

OH(V)

V

IH(D)

V

IL(D)

NOTE 5: Characteristics are for surface-mount packages only.

Quiet output, maximum dynamic V Quiet output, minimum dynamic V Quiet output, minimum dynamic V High-level dynamic input voltage 2.31 V Low-level dynamic input voltage 0.99 V

= 3.3 V, C

CC

= 50 pF, TA = 25°C (see Note 5)

L

OL OL OH

operating characteristics, TA = 25°C

PARAMETER TEST CONDITIONS V

p

= 50 pF,f = 10 MHz

L

SN74LV367A

MIN TYP MAX

0.5 0.8 V

–0.2 –0.8 V

3 V

TYP UNIT

CC

3.3 V 14.9 5 V 17.4

p

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

From Output

Under Test

(see Note A)

SN54LV367A, SN74LV367A

HEX BUFFERS AND LINE DRIVERS

WITH 3-STATE OUTPUTS

SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999

PARAMETER MEASUREMENT INFORMATION

V

Test Point

C

L

From Output

Under Test

(see Note A)

C

L

RL = 1 kΩ

S1

CC

Open

GND

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open Drain

Open

V

CC

GND V

CC

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

t

w

Input

In-Phase

Output

Out-of-Phase

Output

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. t F. t

G. t

50% V

CC

VOLTAGE WAVEFORMS

PULSE DURATION

50% V

CC

t

PLH

50% V

CC

t

PHL

50% V

CC

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

PLZ PZL PHL

and t and t

and t

are the same as t

PHZ

are the same as ten.

PZH

are the same as tpd.

PLH

3-STATE AND OPEN-DRAIN OUTPUTS

50% V

CC

dis

t

PHL

50% V

t

PLH

50% V

.

LOAD CIRCUIT FOR

V

CC

0 V

V

CC

0 V

V

OH

CC

V

OL

V

OH

CC

V

OL

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at V

(see Note B)

Waveform 2

(see Note B)

CC

Output

S1 at GND

50% V

CC

t

CC

h

50% V

CC

t

PLZ

VOL + 0.3 V

t

PHZ

VOH – 0.3 V

t

su

50% V

CC

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

50% V

CC

t

PZL

50% V

t

PZH

50% V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

V

CC

0 V

V

CC

0 V

V

CC

0 V

≈V

V

OL

V

OH

≈0 V

CC

Figure 1. Load Circuit and Voltage Waveforms

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7

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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

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Texas Instruments SN74LV367AD, SN74LV367ADBR, SN74LV367ADGVR, SN74LV367ADR, SN74LV367ANSR Datasheet

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