SN74LV32A-Q1
OUTPUT
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SCLS516C − JULY 2003 − REVISED FEBRUARY 2008
D Qualified for Automotive Applications
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D 2-V to 5.5-V V
D Max t
D Typical V
<0.8 V at V
D Typical V
>2.3 V at V
of 6.5 ns at 5 V
pd
OLP
OHV
Operation
CC
(Output Ground Bounce)
= 3.3 V, TA = 25°C
CC
(Output VOH Undershoot)
= 3.3 V, TA = 25°C
CC
PW PACKAGE
1A
1B
1Y
2A
2B
2Y
GND
(TOP VIEW)
1
2
3
4
5
6
7
D Supports Mixed-Mode Voltage Operation on
All Ports
D I
description/ordering information
Supports Partial-Power-Down Mode
off
Operation
These quadruple 2-input positive-OR gates are designed for 2-V to 5.5-V VCC operation.
The SN74LV32A performs the Boolean function Y + A ) BorY+ A
This device is fully specified for partial-power-down applications using I
• B in positive logic.
. The I
off
preventing damaging current backflow through the device when it is powered down.
V
14
CC
13
4B
12
4A
11
4Y
10
3B
9
3A
8
3Y
circuitry disables the outputs,
off
ORDERING INFORMATION
T
A
−40°C to 105°C TSSOP − PW Tape and reel SN74LV32ATPWRQ1 LV32AT
†
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at http://www.ti.com.
‡
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
PACKAGE
logic diagram, each gate (positive logic)
A
B
‡
FUNCTION TABLE
(each gate)
INPUTS
A B
H X H
X HH
L L L
ORDERABLE
PART NUMBER
OUTPUT
Y
†
TOP-SIDE
MARKING
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2008, Texas Instruments Incorporated
1
SN74LV32A-Q1
mA
mA
∆t/∆v
Input transition rise or fall rate
ns/V
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SCLS516C − JULY 2003 − REVISED FEBRUARY 2008
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
(see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
Voltage range applied to any output in the high-impedance
or power-off state, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
(see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(see Notes 1 and 2) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(VI < 0) −20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3) 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
CC
V
IH
V
IL
V
I
V
O
I
OH
I
OL
∆t/∆v Input transition rise or fall rate
T
A
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5.5 V
VCC = 2 V 1.5
High-level input voltage
Low-level input voltage
Input voltage 0 5.5 V
Output voltage 0 V
High-level output current
Low-level output current
Operating free-air temperature −40 105 °C
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
VCC = 2.3 V to 2.7 V V
V
= 3 V to 3.6 V V
CC
VCC = 4.5 V to 5.5 V V
VCC = 2 V 0.5
VCC = 2.3 V to 2.7 V V
V
= 3 V to 3.6 V V
CC
VCC = 4.5 V to 5.5 V V
VCC = 2 V −50 µA
VCC = 2.3 V to 2.7 V −2
V
= 3 V to 3.6 V −6
CC
VCC = 4.5 V to 5.5 V −12
VCC = 2 V 50 µA
VCC = 2.3 V to 2.7 V 2
V
= 3 V to 3.6 V 6
CC
VCC = 4.5 V to 5.5 V 12
VCC = 2.3 V to 2.7 V 200
V
= 3 V to 3.6 V 100
CC
VCC = 4.5 V to 5.5 V 20
CC
CC
CC
× 0.7
× 0.7
× 0.7
CC
CC
CC
× 0.3
× 0.3
× 0.3
CC
V
V
V
mA
mA
ns/V
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LV32A-Q1
FROM
TO
LOAD
FROM
TO
LOAD
FROM
TO
LOAD
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SCLS516C − JULY 2003 − REVISED FEBRUARY 2008
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
IOH = −50 µA 2 V to 5.5 V VCC−0.1
V
OH
V
OL
I
I
I
CC
I
off
C
i
IOH = −2 mA 2.3 V 2
IOH = −6 mA 3 V 2.48
IOH = −12 mA 4.5 V 3.8
IOL = 50 µA 2 V to 5.5 V 0.1
IOL = 2 mA 2.3 V 0.4
IOL = 6 mA 3 V 0.44
IOL = 12 mA 4.5 V 0.55
VI = 5.5 V or GND 0 to 5.5 V ±1 µA
VI = VCC or GND, IO = 0 5.5 V 20 µA
VI or VO = 0 to 5.5 V 0 5 µA
VI = VCC or GND
V
CC
3.3 V 3.3
5 V 3.3
MIN TYP MAX UNIT
V
V
pF
switching characteristics over recommended operating free-air temperature range,
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
V
CC
T
= 25°C
PARAMETER
t
pd
FROM TO LOAD
(INPUT)
A or B Y CL = 50 pF 9.6 16.2 1 20 ns
(OUTPUT)
CAPACITANCE
A
MIN TYP MAX
MIN MAX UNIT
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
T
= 25°C
PARAMETER
t
pd
FROM TO LOAD
(INPUT)
A or B Y CL = 50 pF 6.9 11.4 1 13 ns
(OUTPUT)
CAPACITANCE
A
MIN TYP MAX
MIN MAX UNIT
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
T
= 25°C
A
MIN TYP MAX
MIN MAX UNIT
PARAMETER
t
pd
FROM TO LOAD
(INPUT)
A or B Y CL = 50 pF 4.9 7.5 1 8.5 ns
(OUTPUT)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CAPACITANCE
3
SN74LV32A-Q1
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SCLS516C − JULY 2003 − REVISED FEBRUARY 2008
noise characteristics, V
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
NOTE 5: Characteristics are for surface-mount packages only.
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage 2.31 V
Low-level dynamic input voltage 0.99 V
= 3.3 V, CL = 50 pF, TA = 25°C (see Note 5)
CC
PARAMETER MIN TYP MAX UNIT
OL
OL
OH
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS V
C
Power dissipation capacitance CL = 50 pF, f = 10 MHz
pd
0.2 0.8 V
−0.1 −0.8 V
3.1 V
TYP UNIT
CC
3.3 V 9.5
5 V 11.5
pF
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
(see Note A)
SN74LV32A-Q1
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SCLS516C − JULY 2003 − REVISED FEBRUARY 2008
PARAMETER MEASUREMENT INFORMATION
V
Test
Point
C
L
From Output
Under Test
C
L
RL = 1 kΩ
S1
(see Note A)
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
t
w
Input
50% V
CC
50% V
VOLTAGE WAVEFORMS
PULSE DURATION
Input
In-Phase
Output
Out-of-Phase
Output
t
t
PLH
PHL
50% V
CC
50% V
50% V
50% V
CC
CC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z
D. The outputs are measured one at a time, with one input transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PHL
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
and t
are the same as tpd.
PLH
dis
.
H. All parameters and waveforms are not applicable to all devices.
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
Timing Input
V
CC
CC
Data Input
0 V
V
CC
t
PHL
50% V
t
PLH
50% V
CC
CC
0 V
V
V
V
V
CC
OH
OL
OH
OL
Output
Control
Output
Waveform 1
S1 at V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
50% V
CC
t
t
su
50% V
CC
h
50% V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PZH
50% V
50% V
CC
50% V
CC
CC
50% V
t
VOL + 0.3 V
t
VOH − 0.3 V
CC
PLZ
PHZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
= 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
O
V
CC
0 V
V
CC
0 V
V
CC
0 V
≈V
V
OL
V
OH
≈0 V
CC
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com 29-Dec-2009
PACKAGING INFORMATION
Orderable Device Status
SN74LV32ATPWRG4Q1 ACTIVE TSSOP PW 14 2000 Green (RoHS &
SN74LV32ATPWRQ1 ACTIVE TSSOP PW 14 2000 Green (RoHS &
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
no Sb/Br)
no Sb/Br)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-3-260C-168 HR
(3)
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV32A-Q1 :
Catalog: SN74LV32A
•
Enhanced Product: SN74LV32A-EP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 1
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