Texas Instruments SN74LV32AD, SN74LV32ADBLE, SN74LV32ADBR, SN74LV32ADGVR, SN74LV32ADR Datasheet
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SN54LV32A, SN74LV32A
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS385B – SEPTEMBER 1997 – REVISED NOVEMBER 1999
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Typical V
(Output Ground Bounce)
OLP
< 0.8 V at VCC, TA = 25°C
D
Typical V
> 2 V at V
D
Latch-Up Performance Exceeds 250 mA Per
(Output VOH Undershoot)
OHV
, TA = 25°C
CC
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)
description
These quadruple 2-input positive-OR gates are
designed for 2-V to 5.5-V VCC operation.
The ’L V32A devices perform the Boolean function
Y+A)BorY+A
The SN54LV32A is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74LV32A is characterized for
operation from –40°C to 85°C.
• B in positive logic.
SN74LV32A. . . D, DB, DGV, NS, OR PW PACKAGE
SN54LV32A...J OR W PACKAGE
(TOP VIEW)
NC
14
13
12
11
10
9
8
V
3Y
CC
V
4B
4A
4Y
3B
3A
3Y
4B
18
17
16
15
14
3A
CC
4A
NC
4Y
NC
3B
1A
1
1B
2
1Y
3
2A
4
2B
5
6
2Y
GND
SN54LV32A. . . FK PACKAGE
1Y
NC
2A
NC
2B
NC – No internal connection
7
(TOP VIEW)
1B1ANC
3212019
4
5
6
7
8
910111213
2Y
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
FUNCTION TABLE
(each gate)
INPUTS
A B
H X H
X HH
L L L
OUTPUT
Y
Copyright 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54LV32A, SN74LV32A
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS385B – SEPTEMBER 1997 – REVISED NOVEMBER 1999
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
†
1A
1B
2A
2B
3A
3B
4A
4B
1
2
4
5
9
10
12
13
≥ 1
3
1Y
6
2Y
8
3Y
11
4Y
logic diagram, each gate (positive logic)
A
B
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
Package thermal impedance, θJA (see Note 3): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
‡
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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