Datasheet SN74LV273ADBR, SN74LV273ADGVR, SN74LV273ADW, SN74LV273APWR Datasheet (Texas Instruments)
OUTPUT
SN54LV273A, SN74LV273A
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS399A – APRIL 1998 – REVISED AUGUST 1998
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Typical V
< 0.8 V at V
D
Typical V
> 2 V at V
D
Latch-Up Performance Exceeds 250 mA Per
(Output Ground Bounce)
OLP
CC, TA
OHV
CC
= 25°C
(Output VOH Undershoot)
, TA = 25°C
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (DW, NS), Shrink
SN74LV273A. . . DB, DGV, DW, NS, OR PW PACKAGE
SN54LV273A...J OR W PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
Small-Outline (DB), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Flat (W) Packages, Chip
SN54LV273A. . . FK PACKAGE
(TOP VIEW)
Carriers (FK), and DIPs (J)
CC
description
The ’LV273A devices are octal D-type flip-flops
designed for 2-V to 5.5-V V
These devices are positive-edge-triggered
flip-flops with direct clear (CLR
at the data (D) inputs meeting the setup time
operation.
CC
) input. Information
2D
2Q
3Q
3D
4D
1D1QCLR
3212019
4
5
6
7
8
910111213
V
8Q
18
8D
17
7D
16
7Q
15
6Q
14
6D
requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a particular voltage level and
4Q
GND
CLK
5Q
5D
is not directly related to the transition time of the
positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect
at the output.
The SN54LV273A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LV273A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each flip-flop)
INPUTS
CLK D
CLR
L X X L
H ↑ HH
H↑LL
HLXQ
OUTPUT
Q
0
Copyright 1998, Texas Instruments Incorporated
1
SN54LV273A, SN74LV273A
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS399A – APRIL 1998 – REVISED AUGUST 1998
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
CLR
CLK
1D
2D
3D
4D
5D
6D
7D
8D
1
11
3
4
7
8
13
14
17
18
R
C1
1D
logic diagram (positive logic)
CLK
1D
3 4 7 8 13 14 17 18
11
1D
C1
R
2D
1D
C1
R
3D
1D
R
C1
4D
5D
1D
C1
R
1D
R
C1
12
15
16
19
2
1Q
5
2Q
6
3Q
9
4Q
5Q
6Q
7Q
8Q
6D
1D
C1
R
7D
1D
R
C1
8D
1D
C1
R
CLR
1
2 5 6 9 12 15 16 19
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
VIHHigh-level input voltage
V
VILLow-level input voltage
V
IOHHigh-level output current
IOLLow-level output current
SN54LV273A, SN74LV273A
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS399A – APRIL 1998 – REVISED AUGUST 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
†
DGV package 146°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 100°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 4)
SN54LV273A SN74LV273A
MIN MAX MIN MAX
V
V
V
∆t/∆v Input transition rise or fall rate
T
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5.5 2 5.5 V
CC
VCC = 2 V 1.5 1.5
p
p
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 V
O
p
p
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7
VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7
VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7
VCC = 2 V 0.5 0.5
VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3
VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3
VCC = 4.5 V to 5.5 V VCC × 0.3 VCC × 0.3
CC
VCC = 2 V –50 –50 µA
VCC = 2.3 V to 2.7 V –2 –2
VCC = 3 V to 3.6 V –6 –6
VCC = 4.5 V to 5.5 V –12 –12
VCC = 2 V 50 50 µA
VCC = 2.3 V to 2.7 V 2 2
VCC = 3 V to 3.6 V 6 6
VCC = 4.5 V to 5.5 V 12 12
VCC = 2.3 V to 2.7 V 0 200 0 200
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V 0 20 0 20
, literature number SCBA004.
0 100 0 100
0 V
CC
V
mA
mA
ns/V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54LV273A, SN74LV273A
PARAMETER
TEST CONDITIONS
V
UNIT
V
V
V
V
UNIT
twPulse duration
ns
t
S
CLK↑
ns
UNIT
twPulse duration
ns
t
S
CLK↑
ns
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS399A – APRIL 1998 – REVISED AUGUST 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV273A SN74LV273A
MIN TYP MAX MIN TYP MAX
I
I
I
C
OH
OL
I
CC
off
i
CC
IOH = –50 µA 2 V to 5.5 V VCC–0.1 VCC–0.1
IOH = –2 mA 2.3 V 2 2
IOH = –6 mA 3 V 2.48 2.48
IOH = –12 mA 4.5 V 3.8 3.8
IOL = 50 µA 2 V to 5.5 V 0.1 0.1
IOL = 2 mA 2.3 V 0.4 0.4
IOL = 6 mA 3 V 0.44 0.44
IOL = 12 mA 4.5 V 0.55 0.55
VI = VCC or GND 5.5 V ±1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 20 20 µA
VI or VO = 0 to 5.5 V 0 V 5 5 µA
VI = VCC or GND 3.3 V 2 2 pF
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV273A SN74LV273A
MIN MAX MIN MAX MIN MAX
CLR low 6.5 7 7
CLK high or low 7 8.5 8.5
su
t
h
etup time, data before
Hold time, data after CLK↑ 0.5 1 1 ns
Data 8.5 10.5 10.5
CLR inactive 4 4 4
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV273A SN74LV273A
MIN MAX MIN MAX MIN MAX
CLR low 5 6 6
CLK high or low 5 6.5 6.5
su
t
h
etup time, data before
Hold time, data after CLK↑ 1 1 1 ns
Data 5.5 6.5 6.5
CLR inactive 2.5 2.5 2.5
= 2.5 V ± 0.2 V
CC
= 3.3 V ± 0.3 V
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
twPulse duration
ns
t
S
CLK↑
ns
PARAMETER
UNIT
f
MH
C
pF
ns
PARAMETER
UNIT
f
MH
C
pF
ns
SN54LV273A, SN74LV273A
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS399A – APRIL 1998 – REVISED AUGUST 1998
timing requirements over recommended operating free-air temperature range, V
CC
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV273A SN74LV273A
MIN MAX MIN MAX MIN MAX
CLR low 5 5 5
CLK high or low 5 5 5
su
t
h
etup time, data before
Hold time, data after CLK↑ 1 1 1 ns
Data 4.5 4.5 4.5
CLR inactive 2 2 2
switching characteristics over recommended operating free-air temperature range,
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAP ACITANCE
max
tpd* CLK Q
t
* CLR Q
PHL
t
pd
t
PHL
†
t
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
Skew between any two outputs of the same package switching in the same direction
CLK Q 12.9 22.1 1 25 1 25
CLR Q
CL = 15 pF* 55 95 45 45
CL = 50 pF 45 75 40 40
p
= 15
L
CL = 50 pF
TA = 25°C SN54LV273A SN74LV273A
MIN TYP MAX MIN MAX MIN MAX
10.4 18.3 1 20.5 1 20.5
10.3 19 1 21 1 21
13.1 22.8 1 25.5 1 25.5
2 2
= 5 V ± 0.5 V
z
ns
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAP ACITANCE
max
tpd* CLK Q
t
* CLR Q
PHL
t
pd
t
PHL
†
t
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
Skew between any two outputs of the same package switching in the same direction
CLK Q 9.1 17.1 1 19.5 1 19.5
CLR Q
CL = 15 pF* 75 140 65 65
CL = 50 pF 50 110 45 45
p
= 15
L
CL = 50 pF
TA = 25°C SN54LV273A SN74LV273A
MIN TYP MAX MIN MAX MIN MAX
7.1 13.6 1 16 1 16
6.9 13.6 1 16 1 16
8.7 17.1 1 19.5 1 19.5
1.5 1.5
z
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54LV273A, SN74LV273A
PARAMETER
UNIT
f
MH
C
pF
ns
PARAMETER
UNIT
C
d
Power dissi ation ca acitance
C
L
MHz
F
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS399A – APRIL 1998 – REVISED AUGUST 1998
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAP ACITANCE
max
tpd* CLK Q
t
* CLR Q
PHL
t
pd
t
PHL
†
t
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
Skew between any two outputs of the same package switching in the same direction
CLK Q 6.2 11 1 12.5 1 12.5
CLR Q
CL = 15 pF* 120 205 100 100
CL = 50 pF 80 160 70 70
p
= 15
L
CL = 50 pF
TA = 25°C SN54LV273A SN74LV273A
MIN TYP MAX MIN MAX MIN MAX
4.8 9 1 10.5 1 10.5
4.7 8.5 1 10 1 10
6 10.5 1 12 1 12
1 1
z
ns
noise characteristics, V
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
NOTE 5: Characteristics are for surface-mount packages only.
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage 2.31 V
Low-level dynamic input voltage 0.99 V
= 3.3 V, CL = 50 pF, TA = 25°C (see Note 5)
CC
OL
OL
OH
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS V
p
p
p
p
= 50 F,f = 10
SN74LV273A
MIN TYP MAX
0.39 0.8 V
–0.36 –0.8 V
2.92 V
TYP UNIT
CC
3.3 V 15.9
5 V 17.1
p
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
(see Note A)
SN54LV273A, SN74LV273A
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS399A – APRIL 1998 – REVISED AUGUST 1998
PARAMETER MEASUREMENT INFORMATION
V
Test
Point
C
L
From Output
Under Test
(see Note A)
C
L
RL = 1 kΩ
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
t
w
Input
Input
In-Phase
Output
Out-of-Phase
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
F. t
G. t
50% V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
50% V
CC
t
PLH
50% V
CC
t
PHL
50% V
CC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
PLZ
PZL
PHL
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PLH
3-STATE AND OPEN-DRAIN OUTPUTS
50% V
50% V
dis
CC
t
PHL
50% V
t
50% V
.
LOAD CIRCUIT FOR
V
CC
CC
0 V
V
CC
0 V
V
OH
CC
V
OL
PLH
V
OH
CC
V
OL
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Waveform 2
(see Note B)
CC
Output
S1 at GND
50% V
CC
t
CC
CC
h
50% V
50% V
CC
VOL + 0.3 V
VOH – 0.3 V
t
su
50% V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
50% V
CC
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
t
PLZ
50% V
t
PHZ
50% V
CC
V
CC
0 V
V
CC
0 V
V
CC
0 V
≈ V
V
OL
V
OH
≈ 0 V
CC
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Loading...